G
Grumble
Hello,
Those who can read French might be interested in the following article:
http://www.x86-secret.com/?option=newsd&nid=845
According to the article, the behavior of the time stamp counter has
recently been modified.
<quote>
The current PRM does not include a complete description for the latest
Intel(r) Pentium(r) 4 Processor TSC operation. Intel is currently
working on a clarification of the Programmers Reference Manual (PRM) in
relation to, but not inclusive of, the following points.
For Intel(r) Pentium(r) 4 Processors with CPUID (Family, Model,
Stepping) greater than 0xF30 the designed implementation of the TSC is
for the counter to operate at a constant rate. This was implemented due
to a request from Operating System Software vendor(s). That rate may be
set by the maximum core-clock to bus-clock ratio of the processor or may
be set by the frequency at which the processor is booted. The specific
processor configuration will determine the exact behavior.
This constant TSC behavior ensures that the duration of each clock tick
is uniform and supports the use of the TSC as a high resolution wall
clock timer even while the processor core may change frequency. The use
of the TSC as a wall clock timer has effectively been prioritized over
other uses of the TSC. This is the architectural behavior for the TSC
moving forward.
To count processor core clocks or to calculate the average processor
frequency Intel recommends using the PMON counters Monitoring data from
the event counters over the period of time for which the average
frequency is required. See PRM Volume 3 Chapter 15 Debugging and
Performance Measuring,Section 15.10.9 and Appendix A Performance
Monitoring Events for details on the Global_Power_Events, event.
</quote>
Those who can read French might be interested in the following article:
http://www.x86-secret.com/?option=newsd&nid=845
According to the article, the behavior of the time stamp counter has
recently been modified.
<quote>
The current PRM does not include a complete description for the latest
Intel(r) Pentium(r) 4 Processor TSC operation. Intel is currently
working on a clarification of the Programmers Reference Manual (PRM) in
relation to, but not inclusive of, the following points.
For Intel(r) Pentium(r) 4 Processors with CPUID (Family, Model,
Stepping) greater than 0xF30 the designed implementation of the TSC is
for the counter to operate at a constant rate. This was implemented due
to a request from Operating System Software vendor(s). That rate may be
set by the maximum core-clock to bus-clock ratio of the processor or may
be set by the frequency at which the processor is booted. The specific
processor configuration will determine the exact behavior.
This constant TSC behavior ensures that the duration of each clock tick
is uniform and supports the use of the TSC as a high resolution wall
clock timer even while the processor core may change frequency. The use
of the TSC as a wall clock timer has effectively been prioritized over
other uses of the TSC. This is the architectural behavior for the TSC
moving forward.
To count processor core clocks or to calculate the average processor
frequency Intel recommends using the PMON counters Monitoring data from
the event counters over the period of time for which the average
frequency is required. See PRM Volume 3 Chapter 15 Debugging and
Performance Measuring,Section 15.10.9 and Appendix A Performance
Monitoring Events for details on the Global_Power_Events, event.
</quote>