I will have to look into this a bit, but
AMD Athlon XP, CPU dual pumps the FSB.
P4, it quad pumps it.
Don't know about core 2 duo.
Meaning, the FSB has an actual speed, and an effective speed.
1600Mhz is so high, it's blatantly an effective speed.
in an estimate.. I would guess that 1600MHz is the quad pumped speed,
and the actual speed of FSB is thus 400Mhz.
Which is the exact same speed as your Memory Bus. whose actual speed
is 400Mhz, and effective speed is 800.
I think quad pumped means sending/receiving 4 bits were data line of
the bus. In each clock cycle.
there's some kind of quartz clock thing in the computer.. which makes
signals HIGH LOW HIGH LOW with time. So if you know GCSE physics, you
get a wave
--------- ---------
!_______!- !_________
a b c
and you can measure a cycle. In physics. it is peak to peak. trough to
trough. or an in between thingy. a-b b-c or a-c.
And a bus is like many lines. I guess 1 bit per line normally.
Dual pumping sends 2 bits per line. Quad pumping sends 4 bits per
line. I think
So the idea is that if a bus operates at say 400MHz, quad pumped.
Then it is equivalent to a bus operating at 1600Mhz without being quad
pumped.
Here is just me thinking.. and it's a new thought. and I am no
engineer. This is probably completely wrong, but
From what I can see.. if 2 buses are communicating..
Say they are same speed, same width.. both same level of pump! so
just regular 1 bit per data line.
one bus could double any one of those factors. And the other bus could
double any one of them to match it. They all seem to be somewhat
equivalent.
Which is why btw, i think the internal memory clock is not pumped..it
uses the width factor. to match the effective speed of the data bus.
..
some of what i have said is probably very wrong.. I hope not too much!
This is quad pumped. The data bus is sampled four times per clock cycle.
I show a slight phase shift in the diagram, because in the real world, it
helps to have setup and hold time with respect to the clock edge.
|<------ 2.5 nanoseconds ------>|
+---------------+ +----
| | |
Clock signal 400MHz ----------------+ +---------------+
______ ______ ______ ______
Data bus is 1600MHz \/ \/ \/ \/ \/
/\______/\______/\______/\______/\
^ ^ ^ ^
| | | |
Sample Sample Sample Sample
The processor data bus has been 64 bits wide for some time, on Intel processors.
That is 8 bytes. At a transfer rate of 1600MHz of data, the theoretical maximum
transfer rate is 1600 * 8 = 12.8GB/sec
DDR2 DRAM has a similar drawing, except for the fact that two pieces of data are
transferred per clock cycle. (Note - I didn't put numbers on this drawing, on
purpose.) The clock here, is whatever clock is used to orchestrate bus transfers.
It may be related to the FSB clock, by a ratio of simple integers. I treat the
memory as a black box, so I cannot see the details.
|<------ ??? nanoseconds ------>|
+---------------+ +----
| | |
Clock signal X MHz ----------------+ +---------------+
______________ ______________
Data bus is 2X MHz \/ \/ \/
/\______________/\______________/\
^ ^
| |
Sample Sample
If you had a DDR2-800 memory, and the sticks are 64 bits wide on the interface
(8 bytes wide), the theoretical maximum transfer rate is 800*8 = 6400MB/sec,
which is why it would be called PC2-6400 memory. On a motherboard chipset
supporting some kind of dual channel concept, both channels deliver 6400MB/sec,
for a possible total of 12800MB/sec. So now my memory subsystem appears to
exactly matches the processor FSB transfer rate.
Now, why doesn't this matter. Well, if you look at a timing diagram for
the bus, no bus is occupied 100% of the time. With DRAM memory, you have to set
up row address and column address, before something can happen. There is a
limit as to how much the operations can be overlapped. So the data bus shown
above, will be idle part of the time.
To see an idling, inefficient memory bus, try PDF page 43. DQ is the
memory data bus. I'm much prefer a longer trace, using real world data,
as that would make it easier to explain why the memory is not 100%
efficient. The kinds of diagrams in a datasheet like this, don't show
how much overlap can be achieved between transactions.
http://download.micron.com/pdf/datasheets/dram/ddr2/512MbDDR2.pdf
So the transfers are all "actual", but the bus may not be occupied on
every cycle. Bus qualification (saying whether there is data present
on the bus, on a given cycle), can be implicit or explicit. Explicit
would be a qualifier signal that says "yup, the data bus is good on
this cycle". (On the Intel FSB, these are called strobes.)
Since the memory bus may not be running 100% of the time, it helps
if we crank the memory bus further than the balance point. That helps
compensate for the dead cycles.
Systems can have other limitations, like the BIU may be limited
in how often it is ready to send stuff across the FSB. The sum
total of these effects, only become apparent when you benchmark,
as that is the easiest way to take all of this stuff into account.
The original posters question, was about a chipset using FBDIMMs.
These have an extra level of bus structure. The chipset datasheet,
without elaboration, only offers one ratio at FSB1600, making the
chipset less flexible than your average desktop. This may be a
performance optimization by Intel, to reduce latency in the
Northbridge.
Paul
