What "Parallel Hz" Really Is

[The little lost angel]

Okay. But I still don't understand what causes leaking. What would
cause the circuits of my design to leak?

Erm, pure law of physics?

 

[George Macdonald]

Please show me where there is a "David Wang" in this thread. There is a
"David Maynard" but I did see any "David Wang"

[email protected] - different thread.

 

[GregS]

+---------------
| Tarjei T. Jensen wrote:
| > Rob Warnock wrote:
| >> The PDP-8/I was fully-parallel, just like the PDP-8, except
| >> that it was the first of the "-8" line to use TTL logic levels
| >> (+3V & 0) instead of the negative ones (-3V & 0) used in the
| >> Classic -8. [It was built out of "M-Series" modules, rather
| >> than the "R/S/T/B-Series".]
...
| > I thought TTL was +5V and 0. Or was this a later development?
|
| The TI 74xx TTL series had a power supply of 5V and gnd (signal
| levels of ~3.6V and .8V)...
+---------------

Technically, yes. I was just rounding off for simplicity. And your
3.6V/0.8V aren't quite correct, either. The 3.6 was a "typical"
high output; the minimum guaranteed output voltage was less. IIRC,

As was I, thought pointing out that TTL covered a lot more than the
TI 74xx series.

<detail snipped>

Also, when driven low, TTL inputs sourced substantial current
(typ. -1.6 mA per "unit load") which had to be sinked by the
outputs. [When driven high, inputs sinked a much smaller current,
~100 uA, IIRC, so a fairly-light static current source ("pullup
resistor") was needed on "open-collector" or "tri-state" busses.]

Yes, the output of true TTL is an NPN emitter. In the low state
there is an emitter current out of the input (negative input
current). As you state, in the high state the emitter is reverese-
biased so there is only leakage current. The DTL variants were
similar, but with a shottky diode replacing the NPN emitter.

+---------------
| BTW, most "TTL" wasn't. The later series ('S', 'AS', 'ALS', 'F',
| and even 'LS' were actually SDTL). My bet is that the DECs were
| DTL too, though I'd love to hear more from Rob.
+---------------

Nope, the original M-Series boards were indeed classic 74xx TTL,
*very* low density, e.g., IIRC, an M206 card comprised only two
7474 chips -- only four flip-flops! Later cards may have used
some 'LS or 'S chips, and definitely added more MSI parts to the
earlier SSI-only mix.

Didn't know DEC used simple standard 74XX TTL that far back.
Thanks.

Lets make sure to call those "Modules" not boards.

I don't see either word in the above. We always called the TTL widgets
"modules", and the things they were mounted to, "cards". Cards
then plugged into "boards", boards mounted to "gates", and gates into
"frames", until the 3080 when multiple logic chips were added to
the top level package (module).

When DEC started they just made modules.

greg

 

[Radium]

Try googeling this thread in the newsgroup I indicated (CSIPHC).

Thanks

 

[chrisv]

Shottky diode logic (thus properly DTL) with a shottky clamped totem-pole
output (not part of "TTL"). IIRC, the origonal 74S series was still TTL
(multiple emitter inputs). It's been too long to remember where the
split was made though. ;-)

I'm pretty darn sure that 74XXXX is all TTL. The S and LS series were
just enhancements with shottky transitors (i.e. shottky clamped
transistors) but they are still TTL.

 

[Keith]

I'm pretty darn sure that 74XXXX is all TTL. The S and LS series were
just enhancements with shottky transitors (i.e. shottky clamped
transistors) but they are still TTL.

No, the later versions have schottky diode logic with schottky
clamped amplifier rather than transistor (emitter) logic (74S
series also had the schottky clamped amplifier).

Circuit diagrams (note: from rusty memory)

TTL (74xx and 74Sxx): Vcc
|
.-.
Vcc | | Vcc
| | |
.-. '-' |
| | | |/
| | +---+-| Q3
'_' | |>
| | |
----- |/ V
A1 0----vv \-----| Q2 -
A1 o----/ Q1 |> +-------o O
| |/
+----+| Q4
| |>
.-. |
| | GND
| |
'-' created by Andy´s ASCII-Circuit
| v1.22.310103 Beta www.tech-chat.de
GND

Schottky clamped TTL has schottky diodes from base to collector on
Q2 and Q4 (IIRC) to prevent saturation.

SDTL (74LSxx, 74ASxx, 74ALSxx, etc.):


VCC VCC
| .-. VCC
.-. | |
| | | | |
| | '-' |/
'-' + -|
| | |>
| | |
A1 o-S<--+ |/ V
+--->S-----| -
A2 o-S<--+ |> +--- O
| |/
+--|
| |>
.-. |
| | GND
| |
'-'
|
GND

Again, Q2 and Q4 are schottky clamped.

 

[Del Cecchi]

No, the later versions have schottky diode logic with schottky
clamped amplifier rather than transistor (emitter) logic (74S
series also had the schottky clamped amplifier).

Circuit diagrams (note: from rusty memory)

TTL (74xx and 74Sxx): Vcc
|
.-.
Vcc | | Vcc
| | |
.-. '-' |
| | | |/
| | +---+-| Q3
'_' | |>
| | |
----- |/ V
A1 0----vv \-----| Q2 -
A1 o----/ Q1 |> +-------o O
| |/
+----+| Q4
| |>
.-. |
| | GND
| |
'-' created by Andy´s ASCII-Circuit
| v1.22.310103 Beta www.tech-chat.de
GND

Schottky clamped TTL has schottky diodes from base to collector on
Q2 and Q4 (IIRC) to prevent saturation.

SDTL (74LSxx, 74ASxx, 74ALSxx, etc.):


VCC VCC
| .-. VCC
.-. | |
| | | | |
| | '-' |/
'-' + -|
| | |>
| | |
A1 o-S<--+ |/ V
+--->S-----| -
A2 o-S<--+ |> +--- O
| |/
+--|
| |>
.-. |
| | GND
| |
'-'
|
GND

Again, Q2 and Q4 are schottky clamped.

The pullup device was often a darlington rather than a npn and a diode

 

[Keith]

The pullup device was often a darlington rather than a npn and a diode

I didn't think so because the output current was limited to
~B(3.6/Rc2). With a darlington there wouldn't be much current
limiting (B^2 *3.6/Rc2).

 

[Spehro Pefhany]

I'm pretty darn sure that 74XXXX is all TTL. The S and LS series were
just enhancements with shottky transitors (i.e. shottky clamped
transistors) but they are still TTL.

Compare the schematics on page 2 of this PDF:
http://www.ee.washington.edu/stores/DataSheets/74ls/74ls00.pdf

The '00 and S00 are TTL; the LS00 is DTL.


Best regards,
Spehro Pefhany

 

[Rich Grise]

+---------------
| Don Lancaster wrote:
| > Rich Grise wrote:
| >> I once built a "TV Typewriter" that used pipelining in the
| >> video data path.
| >>
| > Funny.
| > I once built a TV Typewriter, too.
|
| Well, I _did_ put "TV Typewriter" in quotes - I used a 6845...
+---------------

Uh... I suspect Don was referring to the *original* "TV Typewriter": ;-}

http://www.swtpc.com/mholley/RadioElectronics/TV_Typewriter.htm

Uh, yeah, I think that's why Don chimed in with his quip.

Mine had an 80 x 25 display; I did it with black characters on a white
background, which is really only an inverter. Don's did it all with
discrete TTL, as I remember, so when I did mine all the hard parts
were already done.

(I don't exactly remember if I got the pipelining idea from Don, or from
some AMD data book. ;-) )

Cheers!
Rich

 

[Rich Grise]

If Rich built it, it was a "TV Trypewriter".

Screw you.

 

[chrisv]

Again, Q2 and Q4 are schottky clamped.

That does not make it not TTL...

 

[chrisv]

Compare the schematics on page 2 of this PDF:
http://www.ee.washington.edu/stores/DataSheets/74ls/74ls00.pdf

The '00 and S00 are TTL; the LS00 is DTL.

No. DTL was an older type of logic. 'S00 and 'LS00 are both newer
than '00.

 

[Keith]

That does not make it not TTL...

No, there I was responding to the point about schottky clamps,
there. You've snipped out the part that makes it *NOT* TTL. The
input logic *TRANSISTOR* makes the 74xx series "Transistor-
Transistor Logic". Replace the input transistors with *DIODES* and
it becomes Diode-Transistor Logic, or DTL.

 

[Keith]

No. DTL was an older type of logic. 'S00 and 'LS00 are both newer
than '00.

Sometimes the old becomes new again. The fact is that the 74LSxx
and later families were DTL, no matter what TI called them on the
databook cover.

 

[Spehro Pefhany]

No. DTL was an older type of logic. 'S00 and 'LS00 are both newer
than '00.

"If you call a tail a leg, how many legs does a dog have? Answer:
Four. Calling a tail a leg doesn't make it a leg."
-- Abraham Lincoln


Best regards,
Spehro Pefhany

 

[chrisv]

No, there I was responding to the point about schottky clamps,
there. You've snipped out the part that makes it *NOT* TTL. The
input logic *TRANSISTOR* makes the 74xx series "Transistor-
Transistor Logic". Replace the input transistors with *DIODES* and
it becomes Diode-Transistor Logic, or DTL.

The transistors were not replaced with diodes in S and LS logic. S
and LS is still TTL, schottky clamps and all.

 

[chrisv]

No, there I was responding to the point about schottky clamps,
there. You've snipped out the part that makes it *NOT* TTL. The
input logic *TRANSISTOR* makes the 74xx series "Transistor-
Transistor Logic". Replace the input transistors with *DIODES* and
it becomes Diode-Transistor Logic, or DTL.

I'll dig out my old TI book tonight and look at the schemos.

 

[Keith]

The transistors were not replaced with diodes in S and LS logic. S
and LS is still TTL, schottky clamps and all.

Please read what I've written again. You're simply wrong.

 

[Radium]

Your design? Everything leaks, make more of 'em and they leak more.
You've added a billion more leakers. You can look at David Wang's
excellent "garden hose" analogy in this thread
comp.sys.ibm.pc.hardware.chips.

Okay. I read it. I understand leaking a bit more. I understand that
using 4 billion 1 hz clocks to gain a clock rate of 4 Ghz would leak
[well, any electronic mechanism "leaks" to some extent]. What I don't
understand is why would it leak 3999999999/4000000000ths of the time?