R
redbelly
John said:
Do you mean bandwidth or sample rate?
Mark
Do you mean bandwidth or sample rate?
Mark
D
David Maynard
Jack said:
It is... 'controller'.
D
David Maynard
Rich said:I once built a "TV Typewriter" that used pipelining in the video data
path.
Cheers!
Rich
Going back a year or two there, eh?
R
Rich Grise
Yeah, or 10 or 20. ;-)
<anecdote>
I was working for a video game outfit, repairing video games, like
Pac-Man, and Asteroids, and so on. Some outfit called "Universal"
came up with a game: "Mr. Do!", which they sold in PCB form. At
this time, a new game was about $3,000.00, but "Space Invaders"
and "Pong" and "Asteroids" weren't making the kind of money they
used to, so owner/operators wanted to upgrade their games. "Universal"
sold a kit where you could completely turn a game into a new game
for about $300.00. Plus the monitor, if they were converting a B&W
game.
So, we converted a lot of games, and the owner of the refurbished/
converted game would just throw away the stuff that got replaced,
notably the motherboard, essentially the whole game. So for awhile,
I had a virtually unlimited supply of CPUs, RAMs, EPROMS, all of the
stuff it takes to put a video game on a PCB. I used a Z80 and 6845 for
the memory, I/O, and video control, and a 6502 for the keyboard.
Boy, those were the days! <sigh>
</anecdote>
Cheers!
Rich
T
The little lost angel
Then again, most likely neither do I 
PpP
It's good to see you and the other guys from s.e.b/s.e.d. too!
I've been busy with study and work. Work's mostly design/programming &
marketing leaving very little time to pursuit side hobbies like
electronics. For a while I dropped off the radar on Usenet totally
having had to spend more time tracking local web forums for marketing
purposes and only been back in csiphc for a few months.
Hopefully I'll have some time to drop into seb/sed to bug you guys
with more innate noobish ee questions on some stuff I've been
wondering aboutPPp
<trimmed followup NG>
PpPIt's good to see you and the other guys from s.e.b/s.e.d. too!
I've been busy with study and work. Work's mostly design/programming &
marketing leaving very little time to pursuit side hobbies like
electronics. For a while I dropped off the radar on Usenet totally
having had to spend more time tracking local web forums for marketing
purposes and only been back in csiphc for a few months.
Hopefully I'll have some time to drop into seb/sed to bug you guys
with more innate noobish ee questions on some stuff I've been
wondering about
PPp<trimmed followup NG>
K
krw
Ah, a PDP-8i. (Serial ALU in a parallel computer). <yawn> You do
realize that we can do more than a thousand transistors on a chip
these days (forget the number in a system).
K
krw
She's the patron L'Angel of .chips and only got x-posted here. ;-)
R
Radium
Did PDP-8i use "parallel hz"?
Actually my proposed device is more like a massively-serial one with
clock-rate being the only parallel entity. A billions 1 hz clocks
somehow result in an effective 1 Ghz clock rate.
N number of 1 hz clocks = clock rate of N hz
Everything else is serial
K
krw
I don't even know what "parallel Hz" (Hz is capitalized to honor
the person, BTW) is. It (I believe it was the 'I' was a parallel
processor that had a serial ALU.
Key word: "somehow". In other words, you're clueless.
And you would want to do this, why? (forgetting for a moment that
I don't even know what it is that you're proposing - I doubt you do
either).
Ok, now before you answer this next question, think. What are you
going on about?
R
Radium
Parallel Hz = method using N number of 1 hz clocks to gain a clock rate
of N hz.
http://img56.imageshack.us/img56/2427/clocksignalexample8is.gif
If each clock signal is 1 hz, and you have a billion of them, staggered
such that every 1ns part of the CPU can start, and finish, an
instruction - making the effective 'clock rate' 1 Ghz.
For fun.
A computer that is totally serial except for the frequency aspect. It
has a clock rate of 4 Ghz that is obtained by using 4 billion 1 hz
clocks. But otherwise, it is completely serial.
K
krw
You repeat yourself. You still don't say how you're proposing to
*USE* this to some advantage.
Ans this is good why? What is your proposed gain? You now have a
billion clocks to route (and time), as well as signals. You're
gaining nothing and increasing complexity. Why don't you think up
a new (and workable) way of getting rid of the clocks.
Ah, so it was never intended to have a practical use. ...just so
much more mental masturbation. Try the binary groups.
So you have four billion latches sitting around doing nothing but
leaking for 3999999999/4000000000ths of the time?
R
Radium
krw said:
Why would they leak anymore than normal clocks?
D
daytripper
not even. this has *much* less value than that...
J
John Fields
D
DevilsPGD
R
Radium
DevilsPGD said:
What causes them to leak?
J
John Fields
---
If you have to ask, then you don't know what you're talking about.
If you need some fundamental information it would probably be best
if you posted to sci.electronics.basics, where there are no stupid
questions.
R
Rob Warnock
+---------------
| (e-mail address removed) says...
| > The little lost angel wrote:
| > > Isn't this like taking double/quadruple pumped bus and pipelining to
| > > the extreme?
| >
| > No. Not at all. As I said in another post, my proposed device is
| > completely serial except for the frequency. It uses "parallel hz" but
| > in terms of everything other than frequency, it is totally serial and
| > non-parallel. Only the clock rate is parallel.
|
| Ah, a PDP-8i. (Serial ALU in a parallel computer).
+---------------
You're thinking of the PDP-8/S ["S" for "Serial"].
*Horribly* slow, its main claim to fame was being the first
general-purpose computer to sell for $10,000. The PDP-8/I,
introduced just a couple of years later, had all the speed
of the "Classic" PDP-8 with a price only slightly higher
than the -8/S [and the PDP-8/L was even cheaper]. See:
http://www.faqs.org/faqs/dec-faq/pdp8-models/
The PDP-8/I was fully-parallel, just like the PDP-8, except
that it was the first of the "-8" line to use TTL logic levels
(+3V & 0) instead of the negative ones (-3V & 0) used in the
Classic -8. [It was built out of "M-Series" modules, rather
than the "R/S/T/B-Series".]
Note that the PDP-8 series *did* have a multi-phase clock --
four "TS1-4" clocks (or phases) and four much-shorter "TP1-4"
pulses that overlapped the transitions between the TSn phases.
The TSn phases were generally used as "enables" of some kind,
and the TPn clock pulse that terminated the phase of the same
number were generally used to clock the results of the phase
into some register. In the PDP-8/E (another TTL machine) at least,
the TSn/TPn clocks were generated from a ring or "Johnson" counter,
what today we'd call a "one-hot state machine", running at 20 MHz.
[And, yes, I know the difference between a ring counter and a
Johnson counter -- ISTR that some members of the PDP-8 family
used one and some used the other.] In the PDP-8/E, a normal
instruction took 1.2us or 24 ticks of the ring counter, but
the ring had alterate "sidings", if you will, that permitted
read/modify/write memory cycles to take 28 ticks, or 1.4us, and
extended one of the phases (TS3? TS4?) so that the incremented
[or otherwise modified] results had time to propagate to the bus.
So in a sense, it's probably legitimate to say that the PDP-8
series did use a simple form of the OP's "parallel Hz" clocking.
-Rob
| (e-mail address removed) says...
| > The little lost angel wrote:
| > > Isn't this like taking double/quadruple pumped bus and pipelining to
| > > the extreme?
| >
| > No. Not at all. As I said in another post, my proposed device is
| > completely serial except for the frequency. It uses "parallel hz" but
| > in terms of everything other than frequency, it is totally serial and
| > non-parallel. Only the clock rate is parallel.
|
| Ah, a PDP-8i. (Serial ALU in a parallel computer).
+---------------
You're thinking of the PDP-8/S ["S" for "Serial"].
*Horribly* slow, its main claim to fame was being the first
general-purpose computer to sell for $10,000. The PDP-8/I,
introduced just a couple of years later, had all the speed
of the "Classic" PDP-8 with a price only slightly higher
than the -8/S [and the PDP-8/L was even cheaper]. See:
http://www.faqs.org/faqs/dec-faq/pdp8-models/
The PDP-8/I was fully-parallel, just like the PDP-8, except
that it was the first of the "-8" line to use TTL logic levels
(+3V & 0) instead of the negative ones (-3V & 0) used in the
Classic -8. [It was built out of "M-Series" modules, rather
than the "R/S/T/B-Series".]
Note that the PDP-8 series *did* have a multi-phase clock --
four "TS1-4" clocks (or phases) and four much-shorter "TP1-4"
pulses that overlapped the transitions between the TSn phases.
The TSn phases were generally used as "enables" of some kind,
and the TPn clock pulse that terminated the phase of the same
number were generally used to clock the results of the phase
into some register. In the PDP-8/E (another TTL machine) at least,
the TSn/TPn clocks were generated from a ring or "Johnson" counter,
what today we'd call a "one-hot state machine", running at 20 MHz.
[And, yes, I know the difference between a ring counter and a
Johnson counter -- ISTR that some members of the PDP-8 family
used one and some used the other.] In the PDP-8/E, a normal
instruction took 1.2us or 24 ticks of the ring counter, but
the ring had alterate "sidings", if you will, that permitted
read/modify/write memory cycles to take 28 ticks, or 1.4us, and
extended one of the phases (TS3? TS4?) so that the incremented
[or otherwise modified] results had time to propagate to the bus.
So in a sense, it's probably legitimate to say that the PDP-8
series did use a simple form of the OP's "parallel Hz" clocking.
-Rob
T
Tarjei T. Jensen
Rob said:
Hi,
I thought TTL was +5V and 0. Or was this a later development?
greetings,
K
Keith
Interesting stuff, indeed. I'm certainly not a DECie, so remembered
wrongly. ;-)
The TI 74xx TTL series had a power supply of 5V and gnd (signal levels of
~3.6V and .8V), but that wasn't the only TTL ever to be done. IBM's
TTL, used in the 3080s, was +1.25/-3V with a signal level of gnd to -1.5V,
IIRC. TTL is a circuit topology, rather then a specific product.
BTW, most "TTL" wasn't. The later series ('S', 'AS', 'ALS', 'F', and even
'LS' were actually SDTL). My bet is that the DECs were DTL too, though
I'd love to hear more from Rob. ...maybe continue thos over on AFC.