Memory speed question

[SC Tom]

I have an AMD Phenom II x2 555 3.2GHz Black Edition (Callisto) with 4 cores unlocked, an Asus M4N68T-N V2 MB, and
G.SKILL Ripjaws X Series 4GB (2 x 2GB) 240-Pin DDR3 SDRAM DDR3 1333 (PC3 10666).

According to CPU-Z,
JEDEC timings table CL-tRCD-tRP-tRAS-tRC @ frequency
JEDEC #1 6.0-6-6-17-23 @ 457 MHz
JEDEC #2 7.0-7-7-20-27 @ 533 MHz
JEDEC #3 8.0-8-8-22-31 @ 609 MHz
JEDEC #4 9.0-9-9-25-34 @ 685 MHz

with JEDEC#4 being my default. Adjusting the timings through my BIOS, I'm running it at 8-8-8-22-31 @685MHz (BIOS says
667MHz) without having to change any of the voltages (I would prefer not to).

My question is, assuming the defaults shown for each JEDEC group, would memory running the JEDEC#1 settings be the same,
faster, or slower than the JEDEC#4 settings. I realize the higher the frequency the faster the access, but do the
timings for the slower frequencies make up for the speed of the faster frequencies? IOW, if I went to the JEDEC#1
settings using BIOS adjustments, would the memory be discernibly faster than it is now? I can adjust the speeds to
400MHz, 533MHz, 667MHz, and 800MHz. The CL-tRCD-tRP-tRAS-tRC settings can be just about anything from 0 on up.

Just a FMI (For My Information) question; I've never really looked into memory settings much.
TIA!

 

[Paul]

I have an AMD Phenom II x2 555 3.2GHz Black Edition (Callisto) with 4
cores unlocked, an Asus M4N68T-N V2 MB, and G.SKILL Ripjaws X Series 4GB
(2 x 2GB) 240-Pin DDR3 SDRAM DDR3 1333 (PC3 10666).

According to CPU-Z,
JEDEC timings table CL-tRCD-tRP-tRAS-tRC @ frequency
JEDEC #1 6.0-6-6-17-23 @ 457 MHz
JEDEC #2 7.0-7-7-20-27 @ 533 MHz
JEDEC #3 8.0-8-8-22-31 @ 609 MHz
JEDEC #4 9.0-9-9-25-34 @ 685 MHz

with JEDEC#4 being my default. Adjusting the timings through my BIOS,
I'm running it at 8-8-8-22-31 @685MHz (BIOS says 667MHz) without having
to change any of the voltages (I would prefer not to).

My question is, assuming the defaults shown for each JEDEC group, would
memory running the JEDEC#1 settings be the same, faster, or slower than
the JEDEC#4 settings. I realize the higher the frequency the faster the
access, but do the timings for the slower frequencies make up for the
speed of the faster frequencies? IOW, if I went to the JEDEC#1 settings
using BIOS adjustments, would the memory be discernibly faster than it
is now? I can adjust the speeds to 400MHz, 533MHz, 667MHz, and 800MHz.
The CL-tRCD-tRP-tRAS-tRC settings can be just about anything from 0 on up.

Just a FMI (For My Information) question; I've never really looked into
memory settings much.
TIA!

Initial latency 1/457 * 6 = 13.1 [proportionality analysis, no units]
1/685 * 9 = 13.1

Burst transfer rate, faster with 685MHz.

As Orson says, random access, about the same (as random access is
1/transaction_rate and the transaction rate isn't changing measurably).
Totally random access is never a good thing on modern DRAM, and
especially if you're only using one byte from each transaction
attempted. It takes a lot of cycles to set up a complete transaction.

(This isn't a good diagram, but imagine if you put CL=9 in the diagram.)

http://www.design-reuse.com/news_img/20090219_2.gif

Burst transfers of blocks, on the other hand, screams by comparison.

Another thing that could possibly break on a random walk
through memory, is the TLB cache. The translation lookaside
buffer, translates virtual addresses to physical addresses.
On a TLB miss, a hardware table walk may be required, to
work out a new mapping and load the TLB cache with it.
Normally, you'd hardly care about this, but if you had a program
doing purely random memory accesses, the TLB could be
constantly being purged. And then your data transfer
rate, is further reduced.

So JEDEC#4 makes your block-oriented RAM programs go faster.
For the random programs, like fluid (particle) flow simulators or
event simulators, it probably makes no difference what
you do. You'd want to crank down CAS, but probably
won't get very far by doing it (only a small improvement
by torturing the RAM).

Paul

 

[SC Tom]

I have an AMD Phenom II x2 555 3.2GHz Black Edition (Callisto) with 4 cores unlocked, an Asus M4N68T-N V2 MB, and
G.SKILL Ripjaws X Series 4GB (2 x 2GB) 240-Pin DDR3 SDRAM DDR3 1333 (PC3 10666).

According to CPU-Z,
JEDEC timings table CL-tRCD-tRP-tRAS-tRC @ frequency
JEDEC #1 6.0-6-6-17-23 @ 457 MHz
JEDEC #2 7.0-7-7-20-27 @ 533 MHz
JEDEC #3 8.0-8-8-22-31 @ 609 MHz
JEDEC #4 9.0-9-9-25-34 @ 685 MHz

with JEDEC#4 being my default. Adjusting the timings through my BIOS, I'm running it at 8-8-8-22-31 @685MHz (BIOS
says 667MHz) without having to change any of the voltages (I would prefer not to).

My question is, assuming the defaults shown for each JEDEC group, would memory running the JEDEC#1 settings be the
same, faster, or slower than the JEDEC#4 settings. I realize the higher the frequency the faster the access, but do
the timings for the slower frequencies make up for the speed of the faster frequencies? IOW, if I went to the JEDEC#1
settings using BIOS adjustments, would the memory be discernibly faster than it is now? I can adjust the speeds to
400MHz, 533MHz, 667MHz, and 800MHz. The CL-tRCD-tRP-tRAS-tRC settings can be just about anything from 0 on up.

Just a FMI (For My Information) question; I've never really looked into memory settings much.
TIA!

Initial latency 1/457 * 6 = 13.1 [proportionality analysis, no units]
1/685 * 9 = 13.1

Burst transfer rate, faster with 685MHz.

As Orson says, random access, about the same (as random access is
1/transaction_rate and the transaction rate isn't changing measurably).
Totally random access is never a good thing on modern DRAM, and
especially if you're only using one byte from each transaction
attempted. It takes a lot of cycles to set up a complete transaction.

(This isn't a good diagram, but imagine if you put CL=9 in the diagram.)

http://www.design-reuse.com/news_img/20090219_2.gif

Burst transfers of blocks, on the other hand, screams by comparison.

Another thing that could possibly break on a random walk
through memory, is the TLB cache. The translation lookaside
buffer, translates virtual addresses to physical addresses.
On a TLB miss, a hardware table walk may be required, to
work out a new mapping and load the TLB cache with it.
Normally, you'd hardly care about this, but if you had a program
doing purely random memory accesses, the TLB could be
constantly being purged. And then your data transfer
rate, is further reduced.

So JEDEC#4 makes your block-oriented RAM programs go faster.
For the random programs, like fluid (particle) flow simulators or
event simulators, it probably makes no difference what
you do. You'd want to crank down CAS, but probably
won't get very far by doing it (only a small improvement
by torturing the RAM).

Paul

Thanks to you and Orson for the information. It's kind of what I thought, since what sense would it make if higher
frequency RAM wasn't faster than the old stuff

Thanks again!