Eric said:
I don't think that's true. As long as you get modules made with the lower
density chips (I believe you'd need a 512MB module with 16 chips per side;
so a double-row module), it should work correctly.
-Eric Gross
From the data sheet
• DRAM type: Extended Data Out (EDO) (mobile only) or Synchronous (SDRAM)
DRAM controller optimized for dual/quad-bank SDRAM organization on a row by
row basis
• Memory Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory
rows
• Addressing Type: Symmetrical and Asymmetrical addressing
• Memory Modules supported: Single and double density 3.3V DIMMs
• DRAM device technology: 16 Mbit and 64 Mbit
It's more complicated than the 'simple' specs though. You have to turn to
the design guides.
"The 82443BX when configured with 3 double-sided DIMMs using 64Mbit
technology (using x8 devices) may have a total memory size of 384MB. In
order to achieve 512MB while using the same type of devices, a fourth DIMM
socket must be added which adds extra DQ loading. In order to offset the
heavy loading on the DQ lines, a FET switch mux is recommended to reduce
the loading for memory driving the 82443BX, and vice versa."
Most SOHO main boards, at least originally, implemented the 3 DIMM, 384
Meg, design.
"Workstation and server designs face yet another problem in that 1Gbyte
memory configurations are a mandatory requirement for their customers. In
order to build 256Mbyte DIMMs using present day technology, x4 SDRAM
devices must be used. The loading on the control lines (MA/Bxx, CS#, DQM,
CK, etc.) are now twice the loading of a x8 device. A DIMM which
registers” these control lines must be produced in order to meet 100 MHz
timings (note that a PLL must be added to the registered DIMM and the
additional PLL jitter must be factored into the overall timing analysis)."
'Present day' is 1998, in that context. To which an interesting note:
"Intel is also working with DRAM industry leaders to pull in their
schedules of 128Mbit technology in order to achieve a 256MB DIMM solution.
In addition to this, improvements and standardization of DIMM topologies
are in progress in order to add back margin to the overall timing budget."
The upshot is, BX was not designed with 512MB memory modules in mind and,
indeed, even 256meg modules weren't available. The signal lines just aren't
there to plug 512MB modules into the DIMM slots.