Hi Andy,
Thanks for the posting. Well, typically a process running under Windows
2000 or Windows Server 2003 can access up to 2 GB of memory address space
with some of the memory being physical memory and some being virtual
memory. The more programs (and, therefore, more processes) that run, the
more memory you commit up to the full 2 GB of address space.
Windows 2000 Advanced Server and Windows 2000 Datacenter Server support
memory in excess of 4 gigabytes (GB) of RAM by way of the Intel Physical
Addressing Extension (PAE) specification. Windows 2000 Advanced Server is
limited to 8 GB, and Windows 2000 Datacenter Server is limited to 32 GB.
You can enable PAE in the Boot.ini file. To enable PAE, follow these steps:
Click Start, and then click Run.
Type X:\boot.ini, where X is the drive letter of the location of the boot
files, Ntldr, Boot.ini, and so forth.
Modify the line that corresponds to your operating system by appending the
switch /PAE.
Save the file, and then restart the computer.
Even with PAE enabled, the underlying architecture of the system is still
based on 32-bit linear addresses. This effectively retains the 2 GB of
application space and the 2 GB of kernel mode space because only 4 GB of
addresses are available. However, multiple processes can immediately
benefit from the increased RAM because they are less likely to encounter
physical memory restrictions and begin paging. Additionally, applications
can be modified to use the AWE API to allocate memory outside of the
applications process space, bypassing the 2-GB limit for applications.
MORE INFORMATION
With PAE enabled, the operating system moves from a two-level linear
address translation to a three-level address translation. The extra layer
of translation is what provides access to physical memory beyond 4 GB.
Instead of a linear address being split into three separate fields for
indexing into memory tables, it is split into four separate fields; a 2-bit
field, two 9-bit fields, and a 12-bit field that corresponds to the page
size implemented by Intel Architecture (4 KB).
During a context switch the CR3 register is set by the operating system to
point to a Page directory pointer index that is 2-bits wide. The first two
bits are used as an index into this table, with the resulting value
pointing to a Page directory. The first 9-bit field is then used to index
into the Page directory. The indexed value then points to a Page table. The
second 9-bit field is an index into the Page table. This value points to
the actual page in memory where the desired byte is located. Finding this
byte is a simple matter of using the remaining twelve bits of data to index
into the page.
MORE INFORMATION
With PAE enabled, the operating system moves from a two-level linear
address translation to a three-level address translation. The extra layer
of translation is what provides access to physical memory beyond 4 GB.
Instead of a linear address being split into three separate fields for
indexing into memory tables, it is split into four separate fields; a 2-bit
field, two 9-bit fields, and a 12-bit field that corresponds to the page
size implemented by Intel Architecture (4 KB).
During a context switch the CR3 register is set by the operating system to
point to a Page directory pointer index that is 2-bits wide. The first two
bits are used as an index into this table, with the resulting value
pointing to a Page directory. The first 9-bit field is then used to index
into the Page directory. The indexed value then points to a Page table. The
second 9-bit field is an index into the Page table. This value points to
the actual page in memory where the desired byte is located. Finding this
byte is a simple matter of using the remaining twelve bits of data to index
into the page.
Thanks,
(e-mail address removed)
This posting is provided "AS IS" with no warranties, and confers no rights.
