P55T2P4 TAG RAM Question

[Frank Walker]

I hope someone in this group can guide me.

I am running the subject MOBO with a K6-2 475 mHz (mobile) CPU and the
Steunebrink BIOS (thanks, Jan). It is the Rev. 3.1 board with 512K of
L2 cache on board (no COAST module or socket). FSB is set to 83 mHz.
With a 6x multiplier this gives 498 mHz, a slight overclock for the
CPU. This configuration has been running strong and long (and cool!)
with zero problems from the first moment of powerup.

Until now I have been doing just fine with 64M of RAM. But I need to
double that and go to 128M. This means I must fill the TAG RAM socket
which previously had remained empty.

In my "spare parts" drawer I have several candidates (all identical
one to the other) to fill that empty socket. But the memory ICs I
have (brand is EtronTech) are all rated at 15ns. This is a worry and
the reason for this post.

I know 15ns TAG RAM would be OK if the FSB were set to 66 mHz.

Has anybody had success running TAG RAM this slow (15ns) with an 83
mHz FSB on a P55T2P4? Any opinions out there?

Thanks!!

 

[Max Attar Feingold]

I hope someone in this group can guide me.

I am running the subject MOBO with a K6-2 475 mHz (mobile) CPU and the
Steunebrink BIOS (thanks, Jan). It is the Rev. 3.1 board with 512K of
L2 cache on board (no COAST module or socket). FSB is set to 83 mHz.
With a 6x multiplier this gives 498 mHz, a slight overclock for the
CPU. This configuration has been running strong and long (and cool!)
with zero problems from the first moment of powerup.

Until now I have been doing just fine with 64M of RAM. But I need to
double that and go to 128M. This means I must fill the TAG RAM socket
which previously had remained empty.

In my "spare parts" drawer I have several candidates (all identical
one to the other) to fill that empty socket. But the memory ICs I
have (brand is EtronTech) are all rated at 15ns. This is a worry and
the reason for this post.

I know 15ns TAG RAM would be OK if the FSB were set to 66 mHz.

Has anybody had success running TAG RAM this slow (15ns) with an 83
mHz FSB on a P55T2P4? Any opinions out there?

I've had a T2P4 running for many years with 5ns TAG RAM. The chip id is
GLT725608-15T.

When I had a P233 on this board, I ran it at 83x3 for some time and it
worked fine. I eventually opted for 75x3.5, which also worked fine.

These days, I don't really have the over clocking bug, so the system is
running a K6-III 400MHz at 66x6.

Anyway, I would guess that it will work alright for you. However,
you'll probably want to run memtest86 for a night or two and make sure
everything is stable.

Max Attar Feingold
maf6 at cornell dot edu
http://almonaster.sourceforge.net/mfeingol/

Not speaking for my employer

 

[Frank Walker]

Understood. Thank you, Max.

It has taken me a little while to follow through. As things have
turned out I was not satisfied with the performance of memtest86 (v3)
re its treatment of L2 cache.

I set P55T2P4 board up with the 15ns TAG RAM and 96M of RAM (do not
have the full 128M yet). Moved the TAG RAM jumper to the 2-3
position, as is required for activation above 64M. Upon running
memtest86 I was delighted to discover all 96M of RAM being cached.
Wonderful!

But I was doing this for the first time, and being sometimes a
suspicious individual, I next removed the TAG RAM IC altogether and
again ran memtest86.

Once again, memtest86 declared ALL 96M of RAM to be cached. This is
of course bullshit. There was no TAG RAM plugged in.

To resolve the above it was necessary to run CTCM, a program which
apparently DOES know its way around an old fashioned L2 cache. CTCM
declared the final 32M of RAM to be cached ONLY when the TAG RAM was
plugged in. Otherwise it correctly warned me of my failure to cache
that same 32M. (I like CTCM)

(Recalling earlier concern re TAG RAM speed) before running CTCM I ran
memtest86, with TAG RAM chip in place, for a while in an effort to
test my TAG RAM chip. Memtest86 reassured me re the flawless
operation of the MOBO including especially RAM - no errors were
discovered. But I am not convinced memtest86 was in reality
exercising or testing the TAG RAM, or for that matter the L2 cache.
My gut worries it was merely testing RAM. I should be able to think
my way through this but, so far I cannot.

Anybody out there have enough knowledge of memtest86 to be able to
comment on this matter authoritatively?? All such input would be
gratefully received.

Thanks!

 

[Kevin Hamann]

Understood. Thank you, Max.

It has taken me a little while to follow through. As things have
turned out I was not satisfied with the performance of memtest86 (v3)
re its treatment of L2 cache.

I set P55T2P4 board up with the 15ns TAG RAM and 96M of RAM (do not
have the full 128M yet). Moved the TAG RAM jumper to the 2-3
position, as is required for activation above 64M. Upon running
memtest86 I was delighted to discover all 96M of RAM being cached.
Wonderful!

Just a heads up. 512MB is the most a P/I55T2P4 Rev 3.x board will
take. I have 256MB in mine now and had 128 MB before that.

But I was doing this for the first time, and being sometimes a
suspicious individual, I next removed the TAG RAM IC altogether and
again ran memtest86.

Once again, memtest86 declared ALL 96M of RAM to be cached. This is
of course bullshit. There was no TAG RAM plugged in.

To resolve the above it was necessary to run CTCM, a program which
apparently DOES know its way around an old fashioned L2 cache. CTCM
declared the final 32M of RAM to be cached ONLY when the TAG RAM was
plugged in. Otherwise it correctly warned me of my failure to cache
that same 32M. (I like CTCM)

(Recalling earlier concern re TAG RAM speed) before running CTCM I ran
memtest86, with TAG RAM chip in place, for a while in an effort to
test my TAG RAM chip. Memtest86 reassured me re the flawless
operation of the MOBO including especially RAM - no errors were
discovered. But I am not convinced memtest86 was in reality
exercising or testing the TAG RAM, or for that matter the L2 cache.
My gut worries it was merely testing RAM. I should be able to think
my way through this but, so far I cannot.

Anybody out there have enough knowledge of memtest86 to be able to
comment on this matter authoritatively?? All such input would be
gratefully received.

I'm no authority but consider the following:

All memory tests to the best of my knowledge, including memtest86,
read and write data from the ram to the cpu and back. If it was not
using the L2 cache it would be terribly slow (disable the L2 cache in
the bios and try it if you like). Since the data goes to the cpu and
back to the ram it goes through the L2 cache. If it goes through the
L2 cache and checks the memory, 96MB in your present case, it uses the
tag ram to cache the upper 32 MB. If it gets errors in that 32 MB
it's either the simm module or the tag ram.

If I'm wrong I'm sure one of the real T2P4 gurus will let us know.

Kevin