P4C800-ED and Corsair TwinX1024-3200C2Pro Timing Question

[Michael S.]

These two DIMMs are used on a Asus P4C800-ED motherboard with an Intel 3.2
GHz Northwood. When the BIOS is configured to allow their timings to be
automatically set by SPD, the timings are 2.5-3-3-8 and 4. I have manually
set the timings to 2-3-3-6 and 4 (at which they are rated) and the system is
stable. BUT, am I getting a true 1:1, 800 MHz FSB with the 2-3-3-6 timings?

With the timings set manually in BIOS as 2-3-3-6 here are the results of
three system analysis programs:

Using CPU-Z, the frequency is indicated at 199.9, FSB DRAM as 1:1 and
timings as 2-3-3-6

With PC Wizard, under Chipset, the FSB Speed = 199.9, Bus Speed = 799.6
(QDR) and Memory bus speed = 199.9. TYPE: DDR-SDRAM PC3200, Frequency 200
and timings of 2-3-3-6. Under DIMM A1 it indicates CMZ512-3200C2 with
supported frequencies of 166 MHz and 200 MHz with clocks of 2-3-3-7 each at
166 MHz or clocks of 2.5-3-3-8 each at 200 MHz. The same info for DIMM B1
obviously.

With AIDA32: FSB Properties = real clock 200 MHz (QDR), effective clock 800
MHz and bandwidth 6400 MB/s. Under SPD it shows the highest CAS latency of
2.5 (5.0 ns at 200 MHz) and the 2nd Highest CAS Latency of 2.0 (6.0 ns at
166 MHz)

The data about the tighter timings at 166 MHz vs the looser timings at 200
MHz are confusing to me. Does this mean that at a CAS 2.0 (at which these
DIMMs are rated) they are only running at 166 MHz instead of their rated 200
MHz? If that is true, then the FSB is not running at 800 MHz but at 664 MHz
and I have not achieved the 800 MHz FSB and 1:1 that I desire.

Do I manually set the timings in BIOS at 2-3-3-6 as the DIMMs are rated or
allow the BIOS to automatically apply timings as determined by SPD? Why the
mention of 166 MHz above? I really am confused and I guess this first P4
computer build for me has raised a few questions. Advice to set me straight
will be appreciated.

MikeSp
__________________

 

[Paul]

These two DIMMs are used on a Asus P4C800-ED motherboard with an Intel 3.2
GHz Northwood. When the BIOS is configured to allow their timings to be
automatically set by SPD, the timings are 2.5-3-3-8 and 4. I have manually
set the timings to 2-3-3-6 and 4 (at which they are rated) and the system is
stable. BUT, am I getting a true 1:1, 800 MHz FSB with the 2-3-3-6 timings?

With the timings set manually in BIOS as 2-3-3-6 here are the results of
three system analysis programs:

Using CPU-Z, the frequency is indicated at 199.9, FSB DRAM as 1:1 and
timings as 2-3-3-6

With PC Wizard, under Chipset, the FSB Speed = 199.9, Bus Speed = 799.6
(QDR) and Memory bus speed = 199.9. TYPE: DDR-SDRAM PC3200, Frequency 200
and timings of 2-3-3-6. Under DIMM A1 it indicates CMZ512-3200C2 with
supported frequencies of 166 MHz and 200 MHz with clocks of 2-3-3-7 each at
166 MHz or clocks of 2.5-3-3-8 each at 200 MHz. The same info for DIMM B1
obviously.

With AIDA32: FSB Properties = real clock 200 MHz (QDR), effective clock 800
MHz and bandwidth 6400 MB/s. Under SPD it shows the highest CAS latency of
2.5 (5.0 ns at 200 MHz) and the 2nd Highest CAS Latency of 2.0 (6.0 ns at
166 MHz)

The data about the tighter timings at 166 MHz vs the looser timings at 200
MHz are confusing to me. Does this mean that at a CAS 2.0 (at which these
DIMMs are rated) they are only running at 166 MHz instead of their rated 200
MHz? If that is true, then the FSB is not running at 800 MHz but at 664 MHz
and I have not achieved the 800 MHz FSB and 1:1 that I desire.

Do I manually set the timings in BIOS at 2-3-3-6 as the DIMMs are rated or
allow the BIOS to automatically apply timings as determined by SPD? Why the
mention of 166 MHz above? I really am confused and I guess this first P4
computer build for me has raised a few questions. Advice to set me straight
will be appreciated.

MikeSp

You have to separate the info stored in the SPD EEPROM, which indicates
the "possible", versus the "actual" being used by the board.

You set 2-3-3-6, CPU=200MHz Memory=200MHz.
That means 1:1 ratio between CPU and Memory is being used.
CPU_clock*4 = FSB = 200*4 = FSB800
Mem_clock*2 = DDR = 200*2 = DDR400

So, everything looks good.

The SPD EEPROM on the DIMM reports:

166MHz = 6ns clock period ==> 2.0-3-3-7
200MHz = 5ns clock period ==> 2.5-3-3-8

As the clock speed goes up, the timing must be set "looser".
Inside the memory chips, they have an "analog" timing parameter.
Let us say internally, that the CAS timing is 12 nanoseconds (ns).

When running at 166MHz, 6ns times 2.0 cycles, is 12 nanoseconds.
To give the memory at least the 12 nanoseconds it gets at 166MHz,
at 200MHz they are using 5ns times 2.5 cycles = 12.5 nanoseconds.
The idea is, the product of clock_period*cycle_count must always
be greater than the internal timing parameter, which in this case
I'm just guessing at.

So, if the memory clock was pushed to 250MHz, which is a 4ns clock
period, then the CAS would have to be set to at least 3.0 . That
is assuming, of course, that the memory could actually run at
DDR500.

As for the last parameter, the 7 or 8 in this case, setting that
too tight can cause a burst memory transfer to be aborted. At least
that is what I read on a review site. Using memtest86 or some
other testing program, measure the memory bandwidth as you vary that
parameter. Sometimes a larger setting gives more memory bandwidth.
For example, Wesley Fink, when he writes a review for Anandtech,
will indicate the value that gave him the highest measured memory
bandwidth, and it isn't always a smaller number.

The Corsair datasheet here gives different timings for AMD versus
Intel platforms. That could mean there are Hynix D43 chips in the
module, as I think I read somewhere that the DIMM manufacturers had
to change the ratings to get stability on both platforms.

http://corsairmicro.com/corsair/products/specs/twinx1024-3200c2pro.pdf

Hynix datasheets are here:
http://www.hynix.com/datasheet/eng/dram/dram_sub.jsp?RK=02&RAM_NAME=DDR SDRAM&SUB_RAM=256Mb

(DT_D is DDR400 RAM. Timings are on page 28. Link to datasheet will
change, every time the datasheet revision is changed.)
http://www.hynix.com/datasheet/pdf/dram/HY5DU564(8,16)22DT_D(Rev0.2).pdf

My reason for including a link to an actual memory chip, is so you can
see the "analog" timing values for a real chip. For example, Tras is
40ns, which could be met using 5ns*8 cycles at 200MHz or 6ns*7 cycles
at 166MHz. CAS is stated in a strange way, as a range of clock periods
at a fixed CAS value. In this case CAS3 works at 5ns clock period,
and 3.0*5 = 15ns. Hynix does "bin" chips for companies like Corsair,
so the standard datasheet doesn't represent what you are holding in
your hand.

I don't think Hynix makes the datasheets for its "special" products
available on the web. For example, Hynix announced they had DDR500
ram, but I never could find a datasheet like the sample above. This
is in keeping with never showing info for parts, which exceed the
agreed JEDEC standards (i.e. DDR400).

Paul

 

[Michael S.]

Good Explanation Paul--much appreciated!!!

MikeSp
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