North bridge - MCH core speeds



What core clock speed to N. bridges and MCH's run at? If the FSB I/O bus
speed is double or quad clocked wouldn't the internal clock speed of the
N. bridge or MCH have to be at or above the double or quad clocked FSB
speed? I'd figure the internal registers of the MCH or N. bridge would have
to be filled at the same rate they're being emptied at right?

This newsgroup definitely doesn't see much activity anymore, but then
again, neither does most of usenet these days.

On another note, is Intel's MCH architecture equivalent to a N. bridge
architecture? Because functionally they seem exactly the same.

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