Y
Yugender Reddy
Hi,
I developed drivers for 16 bit PCcard in windows NT 4.0.
I could able to access Attribute memory and Common memory.
But from host side I could able to access only User defined Attribute
memory.
How to access the Card Configuration registers.
In tuple CISTPL_CONFIG, am specifying the Base Address as 0x200
and Register Presence mask as 3.
From my driver through Registry Overrides, am allocating the Base
address of Atribute Mem as 0xd0000 and Base address of Common Mem as
0xd2000.
If I access from 0xd0000, I could able to access the User defined
Attribute Memory only.
As the attribute memory includes both Card Configuration Registers and
CIS details.Why I could able to access only CIS details?
Regarding the CISTPL_CONFIG specified Base Address 0x200,
from where that can be accessed.Whether this 0x200 is considered as
offset for
Attribute Base or it should be directly accessed.
Please help me as I need COR to do S/W reset from my appication as
well as CSR to handle the interrupts.
Thanking you and expecting response very soon.
Yugender
I developed drivers for 16 bit PCcard in windows NT 4.0.
I could able to access Attribute memory and Common memory.
But from host side I could able to access only User defined Attribute
memory.
How to access the Card Configuration registers.
In tuple CISTPL_CONFIG, am specifying the Base Address as 0x200
and Register Presence mask as 3.
From my driver through Registry Overrides, am allocating the Base
address of Atribute Mem as 0xd0000 and Base address of Common Mem as
0xd2000.
If I access from 0xd0000, I could able to access the User defined
Attribute Memory only.
As the attribute memory includes both Card Configuration Registers and
CIS details.Why I could able to access only CIS details?
Regarding the CISTPL_CONFIG specified Base Address 0x200,
from where that can be accessed.Whether this 0x200 is considered as
offset for
Attribute Base or it should be directly accessed.
Please help me as I need COR to do S/W reset from my appication as
well as CSR to handle the interrupts.
Thanking you and expecting response very soon.
Yugender