T
Todd
Hi All,
Question: does the motherboard use the CPU to generate beep codes?
Many thanks,
-T
Question: does the motherboard use the CPU to generate beep codes?
Many thanks,
-T
Y
Yousuf Khan
I think if the CPU itself is the problem, then there's no way for the
CPU to generate a beep code. So likely the beep codes are programmed
into the chipset instead.
Yousuf Khan
P
Paul
Todd said:
As far as I know, beep codes are programmed by the CPU. There are
some registers than need to be programmed. On the motherboards I
have here, if I connected the motherboard SPKR pins to the case
speaker, and just powered up the motherboard, there would be silence
if there was no CPU present.
There have been cases, where something like a short in a RAM module,
can prevent any beep codes from being emitted. Normally, you'd
expect a two beep or three beep error code for "bad RAM", but if
the RAM is bad enough to upset chipset power, it can stop the thing dead.
The BIOS code can run using CPU registers for temporary storage, while
the RAM is being set up. Otherwise, you wouldn't be able to bootstrap
the system, if there was a strict RAM dependency.
The reason the PC generates "one beep" on a good POST, is as a "speaker
test", the equivalent of a "lamp test" on other gear. That's to tell you
the speaker/beeper scheme is good, on each system startup. Then, if some day
you hear nothing, you're more likely to conclude the CPU has failed etc.
Systems can use more than just SPKR. Some Dells have four diagnostic LEDs,
to give a status code. There are motherboards with "Port 80 seven segment
LED display". And Asus used to have "Vocal POST", a Winbond chip capacitively
coupled into one side of the lime green audio output of the onboard sound,
and it would "tell" you what the error code was. The Vocal POST had
pretty poor fidelity, and all you could hear was mumbling, and then
you'd match the "cadence" of the sound you were hearing, to a list
of error messages listed in the manual. I still liked it as a feature,
but the design wasn't the best in terms of fidelity.
Paul
D
dadiOH
Bill said:
That's storage. It is very common to stash values into registers
temporarily. Don't know about now but at one time one CPU had an alternate
set of registers and one could swith back and forth at will. That was real
handy
--
dadiOH
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David H. Lipman
From: "Todd said:
The BIOS generates beep codes in POST. However it takes the CPU to run the BIOS routines.
Y
Yousuf Khan
Here's a list, by BIOS brand:
http://www.computerhope.com/beep.htm
Looks like the CPU itself isn't one of the beep codes.
Yousuf Khan
P
Paul
Bill said:
The BIOS uses register-based code, until the Northbridge memory controller is
programmed. One thing the memory controller must have programmed, is the CAS
value. A special cycle is done by the memory controller, setting up CAS,
so all the memory chips and the controller, "agree" on a common value. While
that programming is going on, the BIOS code will be register based. And the
motherboard doesn't know what value to use, until all the DIMM SPD chips
have been read and processed. You can't "cheat" and load it ahead of time.
It's possible to use processor caches for storage as well, but I'm not
familiar with the details. Some programmers at work, made such a claim,
but I was never able to verify it. I couldn't figure out how that
was possible.
As an example of storage space on a CPU, you have a series of floating point
registers, and the set of those, just gets bigger with each generation.
Paul
C
Char Jackson
Many of the systems I've seen in recent years have a section in the
BIOS where you can specify a CAS value, (among other memory settings),
or you can select the option to "Use SPD". Is using anything other
than "Use SPD" an example of cheating?
I suspect using them isn't the problem. The problem would be
protecting them so that your data isn't quickly overwritten.
P
Paul
Char said:
I'm referring to the hardware somehow knowing in advance, what
the agreed-on CAS timing value should be. It's computed during
POST and loaded into the hardware. The Northbridge, passes the
value to the memory chips, via a special bus cycle, so the memory
can then know the value too. It allows both pieces of hardware
to time events from the same reference event.
Whether the computed value is based on lowest-common-denominator
of SPD values, or based on a BIOS value selected by the user, it
still must be resolved on the fly and loaded into the Northbridge.
And the BIOS code doing that, can't use system memory, until
the simple math involved is completed.
Paul
T
Todd
Hi All,
Thank you for confirming what I suspected.
-T
p.s. the alarm for a bad CPU is an alternating high
low alarm. Sound like a European police siren.
P
Paul
Todd said:
I'd be checking temperatures or the VCore volts reading,
in the hardware monitor page. The CPU isn't necessarily bad,
but the police siren can mean something is wrong with
the "environment".
Paul
T
Todd
Had this happen when an anti virus did a scan. Called
Supermicro and let them listen over the phone. They
said what I was hearing was a fault meaning someone had
reached down and pulled the processor off the board.
Amusing, being as the computer was running fine other
than the high low alarm.
B
BillW50
In
I only ran across three bad CPUs and two of them nothing would happen.
The third was damaged from severe heat. That one passed POST, but it
only would boot XP halfway and then BSOD. My guess is that when switched
to protected mode it would fail.
J. P. Gilliver (John) said:
I only ran across three bad CPUs and two of them nothing would happen.
The third was damaged from severe heat. That one passed POST, but it
only would boot XP halfway and then BSOD. My guess is that when switched
to protected mode it would fail.