Definition of Registered and Buffered SDRAM

[Aaron Gray]

Hi,

I am trying to find out if buffered and registered are the same thing on
PC133 SDRAM.

Wikipedia does not seem to mention anything about "registered" or "buffered"
SDRAM.

Many thanks in advance,

Aaron

 

[Pen]

Hi,

I am trying to find out if buffered and registered are the same thing on
PC133 SDRAM.

Wikipedia does not seem to mention anything about "registered" or "buffered"
SDRAM.

Many thanks in advance,

Aaron

Yes. See Registered Memory.
http://en.wikipedia.org/wiki/Registered_memory

 

[Paul]

Hi,

I am trying to find out if buffered and registered are the same thing on
PC133 SDRAM.

Wikipedia does not seem to mention anything about "registered" or "buffered"
SDRAM.

Many thanks in advance,

Aaron

In this example, the terms are used redundantly, as if they had equal value.
But with modern synchronous memory technologies (SDRAM/DDR/DDR2), registered
is a more precise technical term.

http://www.pricegrabber.com/search_...d=buffered+pc133/rd=1/mode=ink_kwfeed_1/skd=1

With modern memory technologies, the extra interface chip is a register chip,
and the address bus is loaded into the register, before the value is driven
to the memory chips. So the function is definitely "registered". The register
adds a delay of one clock cycle, but the benefit is, that the register chip
drives the load of the memory chips, rather than the poor Northibridge.

http://en.wikipedia.org/wiki/Registered_memory

In the old days, of FPM and EDO DRAM, buffering consisted of an "amplifier".


|\
------| \------ DRAM chip Address buffer on the DIMM, separates
| / the DRAM chip load, from the memory bus
|/


|\
------| \--/\ /\ ---- DRAM chip This one is buffered and "dampered".
| / \/ \/ A 25 ohm series resistor is added.
|/

Modern memory (SDRAM, DDR, DDR2 etc) are clocked memories. They have a
clock signal, which coordinates their operation. The FPM and EDO memories
mentioned above, used RAS and CAS (strobe signals) for their operation,
and were a lot slower. FPM and EDO would allow the above buffering
approach to be used, without screwing up the timing that much. The
buffer had a delay of about 5 nanoseconds. Higher speed memories could
not stand such a technique, due to tighter timing budgets.

A registered DIMM has something like this in the address/control bus path.

+-------+ The square box stores the address
-------|D Q|----- DRAM chip value for one clock cycle. The
| | timing is traceable to the clock
CLK ---|> | signal, and the output side of the
+-------+ register is a separate timing path.

So the older technologies used an actual buffer chip, and the modern
DIMMs now have registers on them.

This is a datasheet for a registered PC133. Page 6 shows a schematic of
the DIMM. Multiple registers live inside a single chip. There are several
register chips in this design. There is also one clock regeneration
chip (PLL), that does clock fanout. The diagram shows they make 10
copies of the clock signal, via the clock chip. The copies are used
for all the synchronous logic on the DIMM (memory chips and registers).

http://download.micron.com/pdf/datasheets/modules/sdram/sd18c32_64_128x72g.pdf

On the Micron site, these are referred to as RDIMMs, and the R stands
for Register. The alternate type are called UDIMMs, where the U
stands for Unbuffered. If you want to find datasheets for the various
types, you may have to select the right type first, to get to the
correct subsection.

HTH,
Paul

 

[Aaron Gray]

Yes. See Registered Memory.
http://en.wikipedia.org/wiki/Registered_memory

Thanks,

Aaron

 

[Aaron Gray]

In this example, the terms are used redundantly, as if they had equal
value.
But with modern synchronous memory technologies (SDRAM/DDR/DDR2),
registered
is a more precise technical term.

http://www.pricegrabber.com/search_...d=buffered+pc133/rd=1/mode=ink_kwfeed_1/skd=1

With modern memory technologies, the extra interface chip is a register
chip,
and the address bus is loaded into the register, before the value is
driven
to the memory chips. So the function is definitely "registered". The
register
adds a delay of one clock cycle, but the benefit is, that the register
chip
drives the load of the memory chips, rather than the poor Northibridge.

http://en.wikipedia.org/wiki/Registered_memory

In the old days, of FPM and EDO DRAM, buffering consisted of an
"amplifier".


|\
------| \------ DRAM chip Address buffer on the DIMM,
separates
| / the DRAM chip load, from the memory
bus
|/


|\
------| \--/\ /\ ---- DRAM chip This one is buffered and "dampered".
| / \/ \/ A 25 ohm series resistor is added.
|/

Modern memory (SDRAM, DDR, DDR2 etc) are clocked memories. They have a
clock signal, which coordinates their operation. The FPM and EDO memories
mentioned above, used RAS and CAS (strobe signals) for their operation,
and were a lot slower. FPM and EDO would allow the above buffering
approach to be used, without screwing up the timing that much. The
buffer had a delay of about 5 nanoseconds. Higher speed memories could
not stand such a technique, due to tighter timing budgets.

A registered DIMM has something like this in the address/control bus path.

+-------+ The square box stores the address
-------|D Q|----- DRAM chip value for one clock cycle. The
| | timing is traceable to the clock
CLK ---|> | signal, and the output side of the
+-------+ register is a separate timing path.

So the older technologies used an actual buffer chip, and the modern
DIMMs now have registers on them.

This is a datasheet for a registered PC133. Page 6 shows a schematic of
the DIMM. Multiple registers live inside a single chip. There are several
register chips in this design. There is also one clock regeneration
chip (PLL), that does clock fanout. The diagram shows they make 10
copies of the clock signal, via the clock chip. The copies are used
for all the synchronous logic on the DIMM (memory chips and registers).

http://download.micron.com/pdf/datasheets/modules/sdram/sd18c32_64_128x72g.pdf

On the Micron site, these are referred to as RDIMMs, and the R stands
for Register. The alternate type are called UDIMMs, where the U
stands for Unbuffered. If you want to find datasheets for the various
types, you may have to select the right type first, to get to the
correct subsection.

Thanks for the info, Paul, always good to know.

I remember RAS and CAS from the old days of DRAM, 4116's and 4164's I think
if my memory serves me correctly ?

We have some old Fujitsu-Siemens Primery 470 servers that use buffered ECC
PC133 SDRAM's and am trying to buy some cheapish memory for them.

Many thanks,

Aaron