Better CPU cache?

[Larc]

Pentium D 945 is available in two versions: C1 with a 4mb cache and the newer D0
with a 2x2mb cache. Obviously, the total cache is the same. Is there any
benefit to having 2mb "reserved" for each core as opposed to having the entire
4mb pooled? Or would any differences be so small as to be unnoticeable in
normal use (as I suspect)?

Thanks for your opinions.

Larc



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[Paul]

Pentium D 945 is available in two versions: C1 with a 4mb cache and the newer D0
with a 2x2mb cache. Obviously, the total cache is the same. Is there any
benefit to having 2mb "reserved" for each core as opposed to having the entire
4mb pooled? Or would any differences be so small as to be unnoticeable in
normal use (as I suspect)?

Thanks for your opinions.

Larc



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There is an article here that discusses Pentium D. It looks like
the 945 is Pressler, and has two separate silicon dies. Cache
coherency requires communication between cores, over the FSB.
The change in notation you are seeing, may just be a clerical
error. If there was a significant change in design (such as
changing from two chunks of silicon, which is easy to manufacture,
to one larger chunk of silicon), generally the family code and
part number would get changed too.

http://en.wikipedia.org/wiki/Pentium_D

According to this, Conroe uses 4MB of shared cache. Which implies
it uses one silicon die for both cores.

http://en.wikipedia.org/wiki/Intel_Core_2

Paul

 

[Larc]

On Sun, 03 Sep 2006 01:36:24 GMT, (e-mail address removed) (Paul) wrote:

| There is an article here that discusses Pentium D. It looks like
| the 945 is Pressler, and has two separate silicon dies. Cache
| coherency requires communication between cores, over the FSB.
| The change in notation you are seeing, may just be a clerical
| error. If there was a significant change in design (such as
| changing from two chunks of silicon, which is easy to manufacture,
| to one larger chunk of silicon), generally the family code and
| part number would get changed too.

Thanks for the reply, Paul.

There was a minor part number change for the D 945 reflecting the spec numbers.
The original 945 was spec# SL9QB and the new one is SL9QQ. But you are correct
about my seeing an error about the cache. Further checking shows both 945s have
2mb per core. So that's not the difference. The only thing that's evident is a
slight difference in the voltage spread from 1.225V-1.312V for the SL9QB and
1.225V-1.325V for the SL9QQ. Maybe that's the only difference.

Larc



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