AGP bus installed on PCI bus?

[valentin tihomirov]

Windows detects AGP bus installed on PCI. How can this be true if AGP
operates at rates much higher that PCI peak performance?

 

[Maxim S. Shatskih]

This only shows how the config space accesses are wired on the motherboard,
and also the lameness of the particular ACPI table.
I saw ACPI tables who claimed that the PS/2 mouse is installed on PCI bus

 

[valentin tihomirov]

But I used to read DDK. It describes device initialization sequence. When
DeviceManager encounters new device it loads proper driver. If detected
device is a bus, enumeration of bus device is requested. This is how device
tree is built. And that is why I wonder; how could PCI bus inform Device
Manager that AGP is one of its children?

 

[Maxim S. Shatskih]

Due to how the config spaces are structured.
BTW - what is the chipset we're speaking about?

 

[Calvin Guan]

Windows detects AGP bus installed on PCI.

Do you mean the AGP bus is sitting behind a PCI-to-PCI bridge or the PCI
root bus?
What's the bus number for the AGP bridge?

 

[Jim]

As far as the hardware is concerned, AGP devices are enumerated on
PCI. The AGP bus has an accelerated data transfer mechanism but the
bus enumeration is all PCI. I am not familiar enough with the
Configuration Manager and AGP but I would think it would be tightly
coupled to the PCI bus enumerator.

Jim

 

[Eliyas Yakub [MSFT]]

From: Davis W (Owner of PCI bus driver)


The root PCI bus in a machine is almost never a real PCI bus. It is a bus
exposed like PCI to software, but is typically a chipset-internal bus that
operates in a chipset-specific way. As a result, AGP can be bridged from
this bus.

 

[valentin tihomirov]

All the chip sets I've seen so far.

 

[Todd Barlow]

From: Davis W (Owner of PCI bus driver)


The root PCI bus in a machine is almost never a real PCI bus. It is a bus
exposed like PCI to software, but is typically a chipset-internal bus that
operates in a chipset-specific way. As a result, AGP can be bridged from
this bus.

I am sorry if this is not directly related to the topic at hand. But
we are performance testing different appliances (Compaq/HP DL360, Dell
1750, etc.) and we find that the faster results (for our tests) are
those boxes that show multiple "PCI BUS" entries at the top-level in
the device manager tree view (by connection)...

I don't think that means that there are that many PCI buses in the
system. The Dell 1750 shows as many as 5 seperate top-level entries!
How could this be?

BTW, our worst performer is one in which only ONE "PCI BUS" entry
exists directly below the ACPI entry, yet the mobo manufacturer calls
what they have a "triple-peer PCI bus architecure". Seems like it
doesn't work too well to me!

Any help in my pursuit of knowledge on this?

Thanks for any help.

 

[Alexander Grigoriev]

PCI bus throughput is much less (20 times) than memory throughput. So it may
make sense to provide a separate PCI bus per each slot or on-board device,
is you don't want the devices sharing PCI bandwidth.

"Eliyas Yakub [MSFT]" <[email protected]> wrote in message

From: Davis W (Owner of PCI bus driver)


The root PCI bus in a machine is almost never a real PCI bus. It is a bus
exposed like PCI to software, but is typically a chipset-internal bus that
operates in a chipset-specific way. As a result, AGP can be bridged from
this bus.

I am sorry if this is not directly related to the topic at hand. But
we are performance testing different appliances (Compaq/HP DL360, Dell
1750, etc.) and we find that the faster results (for our tests) are
those boxes that show multiple "PCI BUS" entries at the top-level in
the device manager tree view (by connection)...

I don't think that means that there are that many PCI buses in the
system. The Dell 1750 shows as many as 5 seperate top-level entries!
How could this be?

BTW, our worst performer is one in which only ONE "PCI BUS" entry
exists directly below the ACPI entry, yet the mobo manufacturer calls
what they have a "triple-peer PCI bus architecure". Seems like it
doesn't work too well to me!

Any help in my pursuit of knowledge on this?

Thanks for any help.

 

[Tim Roberts]

PCI bus throughput is much less (20 times) than memory throughput. So it may
make sense to provide a separate PCI bus per each slot or on-board device,
is you don't want the devices sharing PCI bandwidth.

And that's exactly what PCI-Express does.

 

[public.microsoft.com]

Try scrolling down and you'll find the agp to cpu on pci bus 0. If it works
good why worry? If it doesn't work ,sweat!

 

[valentin tihomirov]

Try scrolling down and you'll find the agp to cpu on pci bus 0.
What does AGP to CPU connector on PCI bus? I't is even more odd than AGP on
PCI. In fact, I don't have such thing. The question is Wintel platform
organisation, not only stupid user question.

 

[public.microsoft.com]

If it really bothers you so much , download the ddk from microsoft and fix
it.