CPU temps stable, then rising w/o load?

[Tam/WB2TT]

In as many words as possible, someone is apparently trying to tell me
that CMOS logic becomes abnormally inefficient as operating frequency
rises, that it's only efficient when idle.

I have designed and built lots of circuits with CMOS logic (thanks to
National Semiconductor's 1988 CMOS logic data book). The family
seemed great for micropower devices including oscillators.

My main question is this:
As operating frequency rises within normal limits, does CMOS become
grossly inefficient compared to other typical forms of logic like
maybe TTL? I don't know much about typical logic families.

From what I recall, the main CMOS power consumption problem occurs
when inputs rise and fall slowly, that it is extremely low power
during normal operation.

Thank you.






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As an example, according to the 1998 Fairchild Advanced Logic Products
Databook, a 74HC244 will draw 3.8ma @ 1MHz, 37.9 ma @ 10 MHz, and 181.5 ma @
70 MHz. For comparison a TTL 74F244 will draw 42.9 ma @ 1 MHz, 69.4 ma @ 10
MHz, and 221.1 ma @ 70 MHz. Some high speed CMOS devices will have a curve
that actually crosses the bipolar curve. For instance a 74VCX244 draws 9.9
ma @ 1 MHz, and 253.8 ma @ 70 MHz.

Tam

 

[JAD]

so now you add more crossposting...to further the OFF TOPIC discussion.?


It has/was a given for many years that when in Bios/Cmos and observing temps
and voltages you were seeing those values while under a 'load'. How much? it
was never really determined from the discussions in this group.

 

[Ken Smith]

[...]

s/Nearly//

No, some comes out on the logic line and thus does not end up as heat
within the chip. Even more generally including the whole system, if you
use the Schottky clamp method to terminate the logic lines, some of the
power goes back onto the rail.

Ever try to put your finger on a modern processor even when it's not
toggling? Leakage is a huge deal in high-end CMOS these days.

The OP was not talking about that sort of CMOS, but point taken.

Both are going to have an AC component of power proportional to
capacitance. TTL will have a higher DC component than SSI CMOS, but
when you get to 130nM and below CMOS starts looking pretty bad too
(though TTL doesn't look at all here .

IIRC: The input capacitance of a TTL gate is a bit smaller than that of a
CMOS gate with the same feature sizes.

 

[John Doe]

Troll.

 

[Mxsmanic]

Really? Yes CMOS logic consumes a tiny amount of power, but that's
not just when idle. If you know of discussion by chip makers like
National Semiconductor, Texas Instruments, Motorola, or any other
well-known manufacturer which supports your reasoning for the
difference in power consumption, I would enjoy reading that.

The original purpose of CMOS was to conserve power. C stands for
"complementary"; it was a type of MOS circuit that used components of
opposite doping schemes such that significant current flowed through
circuits only when they were changing state. Older designs drew a lot
of current even in static state. Originally CMOS was slower than its
predecessors, but constant improvements have made that problem
unimportant (I suppose n- and p-MOS are still faster, but I don't know
to what extent they are still used).

If not for thermal cycling, the degrading stress frequent
temperature variation places on integrated circuits, the halt
instruction would be a better idea.

The excursions in temperature aren't that large; they are much smaller
than those encountered when turning the power off or turning it on. And
the power savings is an important factor to consider.

I'm not saying that there will be a significant decrease in lifespan
even in fast systems like mine which are frequently at 100% CPU
usage. Components are made to run hot. Reducing the temperature at
every opportunity will not necessarily make components last longer.

I think I'll try to keep my components cool, just the same. If Intel
wanted its processors to run hot, it would remove the overtemp
protections.

 

[Mxsmanic]

If you haven't already replied, I think I know what you mean (or
alluding to, or recalling, whatever). During the transition, they suck
current, so you have to make the transition quick.

Yes. Straight NMOS and PMOS draw current all the time, because there
are larger conduction paths even in idle circuits. CMOS paths cancel
themselves out to a large extent except when changing state.

 

[Mxsmanic]

My recollection is that the input transition being slow is what
causes CMOS to suck current.

CMOS is frugal compared to straight NMOS or PMOS, which draws current
continuously.

Complementary metal oxide silicon is extremely efficient even while
operating.

It's efficient, but in the beginning it was very slow. That has
improved a lot, and today the performance hit is too small to negate the
advantages for thermal control and power consumption.

 

[Mxsmanic]

As devices shrink with ever larger numbers of them on die static leakage
has also become a major problem, which is why processors also turn off
power to sections when they're not being used.

During normal operation, or only in power-saving modes?

I haven't kept up much on IC design, significant strides have been made.

 

[John Doe]

John Doe writes:

CMOS is frugal compared to straight NMOS or PMOS, which draws
current continuously.

Your off-topic opinions might be credible (to me) if expressed in an
appropriate group.

It's efficient, but in the beginning it was very slow. That has
improved a lot, and today the performance hit is too small to
negate the advantages for thermal control and power consumption.

In what application?

You make assumptions and sweeping statements about stuff that is
off-topic here.

If you have something to contribute along those lines, why don't you
subscribe to electronics groups?

 

[John Doe]

John Doe writes:

The original purpose of CMOS was to conserve power.

That is true during normal operation as well as during a sleep state.

To convince me that the original purpose of CMOS was to conserve
power during sleep states, you'll have to provide citations or at
least include an appropriate group in your reply.

C stands for "complementary";

I have called it "complementary metal oxide silicon" several times
already.

 

[Mxsmanic]

That is true during normal operation as well as during a sleep state.
Yes.

To convince me that the original purpose of CMOS was to conserve
power during sleep states, you'll have to provide citations or at
least include an appropriate group in your reply.

Sleep states didn't exist when CMOS was invented.

I have called it "complementary metal oxide silicon" several times
already.

CMOS = complementary metal-oxide-_semiconductor_

There are other semiconductors besides silicon, so CMOS may not include
silicon. Germanium is one example.

 

[David Maynard]

In as many words as possible, someone is apparently trying to tell me
that CMOS logic becomes abnormally inefficient as operating frequency
rises, that it's only efficient when idle.

I have designed and built lots of circuits with CMOS logic (thanks to
National Semiconductor's 1988 CMOS logic data book). The family
seemed great for micropower devices including oscillators.

My main question is this:
As operating frequency rises within normal limits, does CMOS become
grossly inefficient compared to other typical forms of logic like
maybe TTL? I don't know much about typical logic families.

From what I recall, the main CMOS power consumption problem occurs
when inputs rise and fall slowly, that it is extremely low power
during normal operation.

Thank you.

You're the only one who's made the irrational leap from being correctly
told that CMOS power consumption increases with operating frequency to a
claim of 'inefficient'.

 

[David Maynard]

David Maynard writes:




During normal operation, or only in power-saving modes?

Certainly in power saving mode but I think some are doing it when operating
as well.

 

[David Maynard]

It is difficult to define "efficiency"when you are talking about logic.

CMOS draws hardly any current when it isn't doing anything,

That's generally true for conventional CMOS applications but, when you get
to the latest and greatest speed demon processors, leakage current becomes
a major issue because of low operating voltages and designing for speed.

The device turns on above gate threshold and off below but it's not an
instantaneous change from on to off at a threshold 'point'. I.E. it's *not*
a 'point' but a curve (exponential). It starts off, more below threshold is
'more' off, and even more is even more 'off', etc. Same for turn on. And,
for speed, you want turn on to be as hard on as possible to reduce Rds. But
that means your threshold needs to be 'comparatively' low so the gate can
be driven well above it.

The tradeoff is the low threshold means the gate cannot be driven as deeply
*off* so leakage currents increase.

With large voltage swings, like in conventional CMOS circuits, you can pick
a threshold that satisfies both but with low voltage swings, as in low
Vcore processors, you run up against not enough voltage swing to drive it
both well above threshold and well below; so you either can't drive them so
deeply off, increasing leakage, or you can't drive them so hard on, slowing
switch speed.

 

[John Doe]

You're the only one who's made the irrational leap from being
correctly told that CMOS power consumption increases with operating
frequency to a claim of 'inefficient'.

Even if that were true, who cares?

The subject was interesting to me and I received definitive replies.
I'm happy.

 

[Matt]

This discussion is way off-topic.

I expect more than a few regulars would like to see you as group
moderator. You could get started putting it to a vote by visiting
http://www.eyrie.org/~eagle/faqs/big-eight.html

 

[David Maynard]

Even if that were true, who cares?

Maybe the person you were trying to accuse of it.

The subject was interesting to me and I received definitive replies.
I'm happy.

Good.

 

[Rich Grise]

It is difficult to define "efficiency"when you are talking about logic.

CMOS draws hardly any current when it isn't doing anything, while TTL
and ECL have a static current drain.

When CMOS switches, it draws current to charge up and discharge its
internal capacitors - which are not all that big - and at high
frequencies some CMOS parts can draw more current than some TTL.

IIRR CMOS data books and data sheets include formulas that let you
estimate current drawn as a function of operating frequency.

Basically, I've always used CMOS when it was fast enough to do what I
needed done.
TTL , ECL and GaAs can be faster, but you start needing massive power
supplies if you have to use them, and loads of cooling fans to get rid
of the heat.

I've heard that there were supercomputers what were actually liquid-cooled.

Cheers!
Rich

 

[John Doe]

....

I expect more than a few regulars would like to see you as group
moderator.

That's really scary.

 

[Mac Cool]

S. Whitmore:

I would appreciate ideas and input on this abrupt shutdown problem

Another possible cause of the abrupt shutdown is fan failure. You may have
a fan that is failing intermittently.