Yonah will have four TDP levels

[YKhan]

New 65nm Pentium-M will have E, T, L, & U power ratings. The FSB will
be either 533Mhz or 666Mhz. The E series will be mostly a DTR chip,
with more than 50W consumption, so it will likely be competing against
AMD Mobile Athlon 64. The T series will likely be in the 25-49W range,
meaning it will compete against AMD Turion ML series. The L series will
be in the 15-24W range, competing against Turion MT series. And the U
series will be less than 14W, probably competing against the Geode
series.

Intel 65nm Yonah CPUs to be named by TDP categories
http://www.digitimes.com/mobos/a20051013A7032.html

 

[Bill Davidsen]

New 65nm Pentium-M will have E, T, L, & U power ratings. The FSB will
be either 533Mhz or 666Mhz. The E series will be mostly a DTR chip,
with more than 50W consumption, so it will likely be competing against
AMD Mobile Athlon 64. The T series will likely be in the 25-49W range,
meaning it will compete against AMD Turion ML series. The L series will
be in the 15-24W range, competing against Turion MT series. And the U
series will be less than 14W, probably competing against the Geode
series.

Unless I misread the article, that U series includes dual-core versions.
Ultra low power dual-core, depending on the actual power drawn by the
U-1500 vs. the single core versions.

 

[Bill Davidsen]

Unless I misread the article, that U series includes dual-core versions.
Ultra low power dual-core, depending on the actual power drawn by the
U-1500 vs. the single core versions.

And to follow my own post after some discussion and thinking, in the U
series the dual-core 1500 runs at 1.06GHz with a 533MHz FSB, while the
766 runs single core at 1.83GHz clock and a faster 667MHz FSB. Other
than the "dual-core" sex appeal, will there be much performance
difference? Doubt it. I wonder what the actual power draw under load
will be for these two chips.

 

[YKhan]

There's been some discussion that Pentium-M's achilles heal in its
power draw is the speed of its FSB. IOW, the faster the FSB is, the
more power the processor has to draw.

So dual-core vs. single-core apparently has little impact on power
draw, it's mainly that FSB.

Yousuf Khan

 

[Del Cecchi]

There's been some discussion that Pentium-M's achilles heal in its
power draw is the speed of its FSB. IOW, the faster the FSB is, the
more power the processor has to draw.

So dual-core vs. single-core apparently has little impact on power
draw, it's mainly that FSB.

Yousuf Khan

What? Are you sure about that? How much power is it?

del cecchi

 

[keith]

There's been some discussion that Pentium-M's achilles heal in its
power draw is the speed of its FSB. IOW, the faster the FSB is, the
more power the processor has to draw.

So dual-core vs. single-core apparently has little impact on power
draw, it's mainly that FSB.

That would be a *first*. Paint me quite skepical!

 

[Del Cecchi]

That would be a *first*. Paint me quite skepical!

note that the front side bus for the pentium m currently is only about a
hundred pins. And the chip powers start at 15 watts. Hard to believe
that more than a couple of watts go into the fsb, although I don't have
my databook handy here to check the power of a gtl+ driver.

 

[daytripper]

note that the front side bus for the pentium m currently is only about a
hundred pins. And the chip powers start at 15 watts. Hard to believe
that more than a couple of watts go into the fsb, although I don't have
my databook handy here to check the power of a gtl+ driver.

One would think the clock trees alone would swamp the sink current of the gtl+
drivers on a typical memory request/response. And fills mean stalled pipes
while waiting for a comparative eternity, so the internals of the chip may use
less power during most bus transactions (conversely, I'll bet Intel's Max
Power programs try to get the miss rate down to zero to do their thing),

Finally, compare the ratio of the number of fets used in the typical p4 cpu
vcc vrd vs what's used for the (fsb) vtt vrd. It's like 6 to 1.

I've been wrong once before ;-) but add me to the extremely skeptical list.

 

[YKhan]

I don't have the link handy right now, I read it a few weeks ago.
Actually let's do a google search, I came up with this little piece:

Pentium M bright star in Intel's fromagerie
http://www.theinquirer.net/?article=19495

 

[Felger Carbon]

That would be a *first*. Paint me quite skepical!

You two are completely overlooking the one important aspect of dual
core: a greatly increased ASP WRT single core. This is of the
utmost importance to the CPU maker. I don't think the maker gives a
rat's hindquarters about anything else.

 

[keith]

You two are completely overlooking the one important aspect of dual
core: a greatly increased ASP WRT single core. This is of the
utmost importance to the CPU maker. I don't think the maker gives a
rat's hindquarters about anything else.

True, ASP is one of the more important specificaitons that HQ looks at.
However, cost is another important issue. A dual core will cost almost
twice a single and the ASP doesn't double, thus margins are lowered. IMO
the only reason Intel is doing duals is because it has no choice.

 

[Del Cecchi]

I don't have the link handy right now, I read it a few weeks ago.
Actually let's do a google search, I came up with this little piece:

Pentium M bright star in Intel's fromagerie
http://www.theinquirer.net/?article=19495

Two more bus bumps to 800MHz would put you at 39W, two more at
51W for a 1066FSB. With appropriate memory, you would be competitive
with the best out there right off the bat. Bumping the core voltage up
a bit, suck up another 10W there, hell, use 20W if you feel the need.
Use this to bump the speed to 2.4GHz, and while you would be in
spitting distance of the best reported 90nm A64 numbers, you would
probably be faster.

theinquirer.net is your source for circuit design information? You gotta
do better than that. The guy pulls the 6w to go 133 MHz out of his
behind. This is a totally meaningless article. Do you really know
anything about hardware?

del

 

[Yousuf Khan]

theinquirer.net is your source for circuit design information? You gotta
do better than that. The guy pulls the 6w to go 133 MHz out of his
behind. This is a totally meaningless article. Do you really know
anything about hardware?

Well perhaps since you're such a hardware design guru, you go ahead and
explain why he and others are observing the power consumption going up
when they simply increase the P-M's FSB?

Yousuf KHan

 

[daytripper]

Well perhaps since you're such a hardware design guru, you go ahead and
explain why he and others are observing the power consumption going up
when they simply increase the P-M's FSB?

Yousuf KHan

Unless the laws of physics were repealed, of course the power consumption will
rise with frequency, all other things being static.

I might have misread what you stated earlier, but I thought the comment was
that the FSB power dominated the consumption of the P-M chip. I still doubt
that is the case...

 

[Yousuf Khan]

Unless the laws of physics were repealed, of course the power consumption will
rise with frequency, all other things being static.

Exactly, but other implication of it is that it seems that the power
consumption rises even if the CPU's own internal clock speed is kept
relatively stable. That is, if it its FSB frequency is raised, but its
own operating clock is kept the same (through FSB multipliers).

I might have misread what you stated earlier, but I thought the comment was
that the FSB power dominated the consumption of the P-M chip. I still doubt
that is the case...

No, but it looks like that as it needs to compete in the higher
performance markets that are currently occupied by the P-4, they're
having to upgrade its FSB, and it's taking a toll on its power
consumption ratings in a disportionate way.

Yousuf Khan

 

[nobody]

Exactly, but other implication of it is that it seems that the power
consumption rises even if the CPU's own internal clock speed is kept
relatively stable. That is, if it its FSB frequency is raised, but its
own operating clock is kept the same (through FSB multipliers).


No, but it looks like that as it needs to compete in the higher
performance markets that are currently occupied by the P-4, they're
having to upgrade its FSB, and it's taking a toll on its power
consumption ratings in a disportionate way.

Yousuf Khan

While this is only a wild guess, but... The lower the FSB clock, the
more time the CPU spends idling while the data is being fetched from
the memory. And it's known that P-M is one of (if not THE ONE) most
energy efficient chips while idling. I even remember reading
somewhere that some idling parts of P-M are turned off until some work
for them arrives. Probably it's not as efficient while doing actual
work.
Again, it's just a speculation. Feel free to correct me if I'm wrong.
NNN

 

[Del Cecchi]

While this is only a wild guess, but... The lower the FSB clock, the
more time the CPU spends idling while the data is being fetched from
the memory. And it's known that P-M is one of (if not THE ONE) most
energy efficient chips while idling. I even remember reading
somewhere that some idling parts of P-M are turned off until some work
for them arrives. Probably it's not as efficient while doing actual
work.
Again, it's just a speculation. Feel free to correct me if I'm wrong.
NNN

There are 32 address lines and 64 data lines, using GTL+. The AC
component is 1/2 CV**2 F times Switching factor. Since the power supply
is 1.2 volts, V**2 is 1.5 at most. Actually somewhat less because the
output doesn't switch rail to rail. The switching factor of address
lines is 1/2 at most since it has a 50-50 chance of randomly changing or
not. Make it 1/4 for data lines because sometime it is reading. Note
that this is worst case. bus nets on a uniprocessor are maybe 20 pf.

So each 10**8 (100 MHz) gives .25 *20*10E-12*1.5*10E-8 or .75mw for
address lines and .375 for data lines. There are 32 address and 64 data
so the AC Component adds up to 24 mw for address plus 24mw for data. per
100 MHz of bus frequency. So at a GHz it is 480 mw.

That's my calculation. Now show me the measurements you have. Or your
calculation. Your inquirerer started out "let's assume the fsb is 6
watts at 533 MHz." and flew off from there.

del

 

[nobody]

There are 32 address lines and 64 data lines, using GTL+. The AC
component is 1/2 CV**2 F times Switching factor. Since the power supply
is 1.2 volts, V**2 is 1.5 at most. Actually somewhat less because the
output doesn't switch rail to rail. The switching factor of address
lines is 1/2 at most since it has a 50-50 chance of randomly changing or
not. Make it 1/4 for data lines because sometime it is reading. Note
that this is worst case. bus nets on a uniprocessor are maybe 20 pf.

So each 10**8 (100 MHz) gives .25 *20*10E-12*1.5*10E-8 or .75mw for
address lines and .375 for data lines. There are 32 address and 64 data
so the AC Component adds up to 24 mw for address plus 24mw for data. per
100 MHz of bus frequency. So at a GHz it is 480 mw.

That's my calculation. Now show me the measurements you have. Or your
calculation. Your inquirerer started out "let's assume the fsb is 6
watts at 533 MHz." and flew off from there.

del

No measurments or calculations. Just pure speculation as openly
mentioned before. Yet, unless I misred something, your calculations
don't explain the matter. Please notice, I am not questioning your
method of calculations, just the result. You arrived at the number of
..48W. Yet the original post was about the difference of tens of watts
when the FSB goes from 533 to 666, all other things equal. And, BTW,
it's not me but one of earlier posters who referred to The Inq.

Rgds,

NNN

 

[Yousuf Khan]

While this is only a wild guess, but... The lower the FSB clock, the
more time the CPU spends idling while the data is being fetched from
the memory. And it's known that P-M is one of (if not THE ONE) most
energy efficient chips while idling. I even remember reading
somewhere that some idling parts of P-M are turned off until some work
for them arrives. Probably it's not as efficient while doing actual
work.
Again, it's just a speculation. Feel free to correct me if I'm wrong.
NNN

Sounds plausible.

Yousuf Khan

 

[Del Cecchi]

No measurments or calculations. Just pure speculation as openly
mentioned before. Yet, unless I misred something, your calculations
don't explain the matter. Please notice, I am not questioning your
method of calculations, just the result. You arrived at the number of
.48W. Yet the original post was about the difference of tens of watts
when the FSB goes from 533 to 666, all other things equal. And, BTW,
it's not me but one of earlier posters who referred to The Inq.

Rgds,

NNN

Yep, it was Yousuf and I think he got it from the inquirer. And I think
they got it by anal extraction. But I don't know either of those things
so that is why I asked whoever put up that number, which appears to be
quadratic in frequency of all things, to fess up.

del