The tutorial that was alluded to by the OP distinguishes between
static power and leakage power. All other references appear to equate
the two concepts, as you have done. I would think that in the "static"
state as many as half the transistors could be ON and therefore
drawing significant current. The rest would be OFF and drawing a
comparatively negligible leakage current????
In classical CMOS curcuits, an "on" or "off" transistor dissipates *no*
power. It's only the ones switching that dissipate power (that's the
classical "dynamic" power). Add in leakage and there is no "off"
transistor. They're all dissipating power, "on" or "off".
OK, so my statement was somewhat ambiguous. I meant that I found only
two online references that mentioned cubic dependency in relation to
power dissipation, and neither of these references talked about static
power or leakage, only dynamic power.
<shrug> Dynamic power is basically a charge pump, pumping power
to-and-fro capicators. These charges (thus current) are linear with
voltage, thus the power quadratic.
Leakage is far from linear. Both leakage current terms (sub-threshold
and gate tunneling) are at least quadratic, thus the power is cubic.
This is the first one:
http://www.intel.com/technology/itj/2003/volume07issue02/art03_pentiumm/p03_awareness.htm
The article discusses the Pentium M processor. It arrives at a cubic
dependency by assuming that frequency is proportional to Vcore. I
confess I don't understand the basis for this assumption.
Not what we're discussing at all. Of course if you raise the frequeny in
proportion to the voltage, the *dynamic* power will cube (P~F*V^2). This
has *nothing* to do with leakage.
This is the second article:
http://books.nap.edu/html/embedded_everywhere/ch2_b3.html
It examines the effects on power dissipation in an existing design when
it is scaled to a new technology. A cubic dependency arises because
newer processes result in lower capacitances and a lower Vcore.
Try searching on *leakage* (even refine that to "sub-threshold" and
"gate tunneling") power, not dynamic power. YOu're confusing yourself
with too many variables.
Well, I understand the concept of leakage from my Uni days, and I
understand how the formula for dynamic power is derived. In the latter
case the energy stored by a capacitor is 1/2 * C * V^2, and this energy
is moved twice during one clock cycle. So power = (1/2 * C * V^2) * 2f =
C * V^2 * f.
Exactly. Now forget that term in the equation. Concentrate on the V/I
charactistics of the devices. As a very simple model, think of leakage as
a diode (of indeterminate forward drop) between the rails. That "leakage"
current will go up exponentially with the voltage, thus its power by the
cube. This is independent of any dynamic power issues, like frequency.
That only leaves the concept of static power as opposed to leakage
power. I don't understand why some references distinguish between the
two, and others do not. How do these parameters differ, ie what are the
mechanisms underlying static power as opposed to leakage?
Forget your notions about "static power". As defined above (circuits
designed to draw DC current) it's a trivial matter. What is now
considered to be "static power" is all power that doesn't conform to the
P~F*V^2 *dynamic* power model. ...and *leakage* swamps that.
