IBM Hurricane chipset leads x86 tpmc 4-way

[Robert Myers]

Greetings,

In the competition for 4-way performance, IBM xSeries 366 with X3
architecture and 3.66MHz Xeons is bested only by a P5 entry from IBM
and an Itanium entry from HP:

http://www.tpc.org/tpcc/results/tpccadvanced3.asp

Filter for 4-way systems and sort on tpmc.

HP's most competitive x86 entry is Opteron, with about 80% of the
performance of the xSeries 366. Whatever the debilities of the
off-chip memory controller and NetBurst, IBM seems to have overcome
them for this benchmark.

RM

 

[Rob Stow]

Greetings,

In the competition for 4-way performance, IBM xSeries 366 with X3
architecture and 3.66MHz Xeons is bested only by a P5 entry from IBM
and an Itanium entry from HP:

http://www.tpc.org/tpcc/results/tpccadvanced3.asp

Filter for 4-way systems and sort on tpmc.

HP's most competitive x86 entry is Opteron, with about 80% of the
performance of the xSeries 366. Whatever the debilities of the
off-chip memory controller and NetBurst, IBM seems to have overcome
them for this benchmark.

More like 87%. And the cost/TPMC is twice as high for the IBM.

Also, if you look at the entries for MicroSoft SQL Server 2000
the results are much closer: 141504 vs 130623, or 92%. Makes
me wonder what the HP box could do if it was running IBM's DB2 -
especially since such a big fuss was made when IBM ported it to
Opteron long before Intel had an AMD64 chip.

 

[George Macdonald]

Greetings,

In the competition for 4-way performance, IBM xSeries 366 with X3
architecture and 3.66MHz Xeons is bested only by a P5 entry from IBM
and an Itanium entry from HP:

http://www.tpc.org/tpcc/results/tpccadvanced3.asp

Filter for 4-way systems and sort on tpmc.

HP's most competitive x86 entry is Opteron, with about 80% of the
performance of the xSeries 366. Whatever the debilities of the
off-chip memory controller and NetBurst, IBM seems to have overcome
them for this benchmark.

I figured Hurricane might be something special. What is Dell to do
now?... beg for a umm, Hurricane? BTW Sun seems to be notably missing
from those charts apart from some somewhat outdated systems. It'd be
interesting to see where the V40z fits in.

 

[Rick Jones]

I figured Hurricane might be something special. What is Dell to
do now?... beg for a umm, Hurricane? BTW Sun seems to be notably
missing from those charts apart from some somewhat outdated systems.
It'd be interesting to see where the V40z fits in.

I seem to recall Sun going on record (pre-Opteron days) about no
longer being terribly impressed with the TPC-C benchmark and stating
that as the reason they were no longer publishing TPC-C results.
There may be some stuff on that topic on their website. I suspect we
would not see TPC-C results for a V40z unless Sun had a change of
heart.

rick jones

 

[Robert Myers]

I figured Hurricane might be something special. What is Dell to do
now?... beg for a umm, Hurricane?

As well as I understand the importance of the chipset, I'm kind of
amazed IBM managed to make so much out of it. I'm sure that somebody
at Intel is paying attention.

RM

 

[Rob Stow]

As well as I understand the importance of the chipset, I'm kind of
amazed IBM managed to make so much out of it. I'm sure that somebody
at Intel is paying attention.

I was wondering about that myself. Until Hurricane, Xeon
couldn't come close to competing with Opteron, and now it looks
like it can actually outperform Opteron. Xeon without Hurricane
is about to become a lot harder to sell, so the prospect of IBM
not sharing Hurricane has probably caused a lot of anxiety at
Intel.

I am looking forward to seeing reviews that show what Hurricane
does for Xeon in other benchmarks.

 

[Yousuf Khan]

I seem to recall Sun going on record (pre-Opteron days) about no
longer being terribly impressed with the TPC-C benchmark and stating
that as the reason they were no longer publishing TPC-C results.
There may be some stuff on that topic on their website. I suspect we
would not see TPC-C results for a V40z unless Sun had a change of
heart.

Well that was because those Ultrasparcs couldn't compete against anybody
either on absolute perf or price/perf. Nowadays, they have a compelling
price/perf story, so you'll likely see them publish again.

Yousuf Khan

 

[Robert Myers]

I was wondering about that myself. Until Hurricane, Xeon
couldn't come close to competing with Opteron, and now it looks
like it can actually outperform Opteron. Xeon without Hurricane
is about to become a lot harder to sell, so the prospect of IBM
not sharing Hurricane has probably caused a lot of anxiety at
Intel.

Intel has become a mystery. One assumes that Intel understands both
the market and the engineering. The surprise for Intel (probably) is
the need to make Xeon competitive in the 4P 64-bit space, a slot it
had reserved for Itanium. Now Intel has to scramble--or maybe they've
already got an answer well along.

There is an interview with an IBM project manager at

http://www.techworld.com/opsys/features/index.cfm?FeatureID=1204

<quote>

At design time, there was a maniacal focus on latency reduction. When
you can cut the time it takes it gets from one point to the next you
can increase performance, so chipset latency has been cut by two and
half times -- down from 265 nanoseconds to 108 nanoseconds.

The way we do that is through snoop bus filtering. It looks across to
the other bus -- because the system uses two buses, two per CPU -- and
the snoop filter does intelligent caching. It can see what's in the
other cache without having to send traffic across the FSB to find out.
Other chipsets cannot do that and need the L3. And if you don't need
L3 cache you shouldn't have to pay the premium to buy it.

</quote>

There's lots of mystification about mainframe features, but that seems
to be the crux of the matter as far as performance is concerned.
Surely Intel can figure it out, one would think.

But the mystery of Intel remains. Whatever are they thinking? I
think they believe they are still going to pull Itanium out of the
fire, that's what I think they're thinking, and I'd still hesitate to
bet against their doing it--technically, at least.

RM

 

[George Macdonald]

As well as I understand the importance of the chipset, I'm kind of
amazed IBM managed to make so much out of it. I'm sure that somebody
at Intel is paying attention.

You mean they must be thinking: "hmmm, dual FSB.... why didn't we think of
that"? It seems like an insanely simple idea but with an entry cost in
development which maybe only IBM could contemplate. It'll be interesting
to see how long they keep it in-house but it looks, at first glance, like
it blows everything else out of the water... in the Intel server sphere
anyway. I figure Mikey's probably taken the week-end off on this one.

 

[Robert Myers]

You mean they must be thinking: "hmmm, dual FSB.... why didn't we think of
that"? It seems like an insanely simple idea but with an entry cost in
development which maybe only IBM could contemplate. It'll be interesting
to see how long they keep it in-house but it looks, at first glance, like
it blows everything else out of the water... in the Intel server sphere
anyway. I figure Mikey's probably taken the week-end off on this one.

I'm really confused about where the dual FSB's are, and I find the
links out there practically unreadable because of the factor of two
problem. Dual (Intel) something or others are going to have dual
FSB's, and one link says X3 takes advantage of the dual FSB of Potomoc
and Cranford. Are the dual FSB's for dual core chips? One link says
the dual FSB makes the Intel FSB competitive with hypertransport.
Dual FSB for a single core chip?

Intel apparently has its own chipset on the way to accommodate its own
dual FSB's, so IBM is apparently just a little bit ahead of the curve
(dual FSB is, after all, bandwidth, and Keith here, who's being
suspiciously silent during this exchange, only wants to talk about
latency as did the IBM project manager previously mentioned elsewhere
in this thread). That is to say, the magic of Hurricane is apparently
latency and not bandwidth, although if you've got a frontside bus
jammed with multiple memory requests, I suppose the two might be
indistinguishable.

I think it's pretty apparent I'm confused, between dual cores, dual
FSB's, factors of two, and all the codenames. What's more, it seems
pretty clear that NetBurst isn't dead. Anybody commented on _that_?

RM

 

[Tony Hill]

I was wondering about that myself. Until Hurricane, Xeon
couldn't come close to competing with Opteron, and now it looks
like it can actually outperform Opteron. Xeon without Hurricane
is about to become a lot harder to sell, so the prospect of IBM
not sharing Hurricane has probably caused a lot of anxiety at
Intel.

Keep in mind that there's a LOT more at play here than just a new
chipset. They are also using new processors with a 33% faster bus
speed than previous XeonMP chips which probably plays a LARGE part in
things. Toss in 64-bit support and I think that a LOT of people are
putting WAY too much emphasis on the chipset itself.

I am looking forward to seeing reviews that show what Hurricane
does for Xeon in other benchmarks.

Let's also wait to see how HP's new DL580G3 and Dell's PowerEdge 6850
servers compare. Both of these servers make use of the new XeonMP
processors but pair it with Intel's i8500 chipset.

Sure, the Hurricane chipset does add a few extra features, but I'm not
convinced that it's in any way the one and only reason why the
performance of these new systems has improved so much.

 

[George Macdonald]

I'm really confused about where the dual FSB's are, and I find the
links out there practically unreadable because of the factor of two
problem. Dual (Intel) something or others are going to have dual
FSB's, and one link says X3 takes advantage of the dual FSB of Potomoc
and Cranford. Are the dual FSB's for dual core chips? One link says
the dual FSB makes the Intel FSB competitive with hypertransport.
Dual FSB for a single core chip?

My *impression* is that instead of having say, two CPUs on a single FSB, as
would be normal with an Intel system, each sits on its own FSB and the
chipset handles the interface, arbitration, snooping etc. between the two.
Beyond that we'll just have to wait for the details I suppose.

Intel apparently has its own chipset on the way to accommodate its own
dual FSB's, so IBM is apparently just a little bit ahead of the curve
(dual FSB is, after all, bandwidth, and Keith here, who's being
suspiciously silent during this exchange, only wants to talk about
latency as did the IBM project manager previously mentioned elsewhere
in this thread). That is to say, the magic of Hurricane is apparently
latency and not bandwidth, although if you've got a frontside bus
jammed with multiple memory requests, I suppose the two might be
indistinguishable.

I think it's pretty apparent I'm confused, between dual cores, dual
FSB's, factors of two, and all the codenames. What's more, it seems
pretty clear that NetBurst isn't dead. Anybody commented on _that_?

You mean Netburst really does exist?

 

[Robert Myers]

Keep in mind that there's a LOT more at play here than just a new
chipset. They are also using new processors with a 33% faster bus
speed than previous XeonMP chips which probably plays a LARGE part in
things. Toss in 64-bit support and I think that a LOT of people are
putting WAY too much emphasis on the chipset itself.

The claimed reductions in latency, "from 265 nanoseconds to 108
nanoseconds," are hard to argue away. If that's an accurate measure
of relative latency and not a hyped-up marketing claim, it will have a
big impact.

Let's also wait to see how HP's new DL580G3 and Dell's PowerEdge 6850
servers compare. Both of these servers make use of the new XeonMP
processors but pair it with Intel's i8500 chipset.

Sure, the Hurricane chipset does add a few extra features, but I'm not
convinced that it's in any way the one and only reason why the
performance of these new systems has improved so much.

"One and only?" Not likely. Most significant? From looking at the
effects of latency on tpc-c in other situations, I'd bet it is. To
see what Intel has as a counter we will, indeed, have to wait and see.

RM

 

[Robert Myers]

My *impression* is that instead of having say, two CPUs on a single FSB, as
would be normal with an Intel system, each sits on its own FSB and the
chipset handles the interface, arbitration, snooping etc. between the two.
Beyond that we'll just have to wait for the details I suppose.

That makes sense.

You mean Netburst really does exist?

Well, apparently, and (although I've given up on code names--there are
just too many right now), there is a possibility it will survive yet
another cycle of reincarnation to 65nm.

RM

 

[Felger Carbon]

Well, apparently, and (although I've given up on code names--there are
just too many right now), there is a possibility it will survive yet
another cycle of reincarnation to 65nm.

Robert, Geo. was making a funny. Netburst is the P4
microarchitecture.

 

[Robert Myers]

Robert, Geo. was making a funny. Netburst is the P4
microarchitecture.

Well, yes, I do understand that. I've lost track of the code names,
but when Intel simultaneously announced the cancellation of a Netburst
project and the start of more than one multiple core Pentium-M
projects, I assumed, and I don't think I was alone, that NetBurst, or
the Pentium 4 architecture, however you wish to refer to it, was at
the end of its life. Apparently not.

RM

 

[daytripper]

Well, yes, I do understand that. I've lost track of the code names,
but when Intel simultaneously announced the cancellation of a Netburst
project and the start of more than one multiple core Pentium-M
projects, I assumed, and I don't think I was alone, that NetBurst, or
the Pentium 4 architecture, however you wish to refer to it, was at
the end of its life. Apparently not.

RM

Hold on to your original thought. It's not wrong.

/daytripper (What's old is new again...)

 

[Robert Myers]

Hold on to your original thought. It's not wrong.

/daytripper (What's old is new again...)

But, if I'm not mistaken, Presler is a NetBurst core and it will
appear at 65 nm. That's one more scale shrink than I thought NetBurst
had to live.

RM

 

[daytripper]

But, if I'm not mistaken, Presler is a NetBurst core and it will
appear at 65 nm. That's one more scale shrink than I thought NetBurst
had to live.

The roadmaps are loaded with sacrificial elements.
P4 is a Dead Chip Walking...

/daytripper

 

[Tony Hill]

My *impression* is that instead of having say, two CPUs on a single FSB, as
would be normal with an Intel system, each sits on its own FSB and the
chipset handles the interface, arbitration, snooping etc. between the two.
Beyond that we'll just have to wait for the details I suppose.

More to the point here, I believe that in the specific case of the
Hurricane chipset it's actually 2 CPUs per bus instead of 4 CPUs as
would normally be the case. This should work fine for the current
XeonMP chips as the Xeon seems to scale ok at this rate. Going by
most benches the 2P Xeon didn't seem to suffer much due to lack of
bandwidth, but 4P Xeon systems got clobbered for this reason.

Of course, the problem here is that dual-core chips should just bring
this bottleneck right back again, since then the "dual FSB" Hurricane
will be back to one bus per 4 cores.