AMD quietly introduces locally-strained silicon process

[Zak]

Also, remember that the strain is
usually quite minute, mechanically seen. But electrically, the strain
is measurable.

I'd think the strain must be huge, though over very short distances only.

If transistors would work better when the chip is mounted under slight
stress that would have been done long ago. Also an Si transistor would
make a handy strain gauge which they seem not to be.

I guess that the strain can be a few percent (see the SiGe lattice) -
which is a lot for a brittle material. But as it is in a very thin layer
and over short distances (areas of stretch and areas of compression
mixed) the overall mechanical effect is negligible.

Also, a thin layer will not store much mechanical energy which means
that cracks will not propagate. Right? Try to stretch something as
brottle as silicon my a few percent and you'll likely have a break
otherwise,


Thomas

 

[Nick Maclaren]

I'd think the strain must be huge, though over very short distances only.

No, because that would lead to too much dislocation.

If transistors would work better when the chip is mounted under slight
stress that would have been done long ago. Also an Si transistor would
make a handy strain gauge which they seem not to be.

I believe that some of the early laboratory experiments did precisely
the former, but it wasn't controllable enough for production. And
the latter has certainly been done - I don't know whether modern
strain gauges work that way, but some did at one stage.


Regards,
Nick Maclaren.

 

[Kai Harrekilde-Petersen]

No, because that would lead to too much dislocation.

Dislocation, and lattice faults during the growth.

I believe that some of the early laboratory experiments did precisely
the former, but it wasn't controllable enough for production. And
the latter has certainly been done - I don't know whether modern
strain gauges work that way, but some did at one stage.

Silicon works very nicely as a strain gauge by way of piezo-electric
effect. Most accelerometers in cars (airbags) use a micro mechanical
bridge with a weight at the end approach, where a diffusion resistor
is placed on the bridge. By measuring the change in resistivity, the
bending (and hence, the acceleration) can be determined.


Kai

 

[Tony Hill]

Nothing to show for it is perhaps an overstatement, unless I am
misreading SpecFP results:

True, it is a bit of an overstatement, but CFP2000 seems to be the
exception rather than the norm. Many other tests have shown little to
no improvement, with a number actually being slower on the Prescott
rather than the Northwood. If all results reflected what we see in
SPEC CPU2000 I don't think people would say much, but as it stands
it's left more than a few people (myself included) wonder just what
the heck all those extra transistors really bought them.

Intel D875PBZ motherboard (3.4 GHz, Pentium 4 processor with HT
Technology) 1308 1300 1 Mar-2004 Config

Intel D875PBZ motherboard (AA-301) (3.4E GHz, Pentium 4 Processor with
HT Technology) 1485 1481 1 core, 1 chip, 1 core/chip (HT
[enabled)] Apr-2004

That's a bigger bump than you get from going to the extreme edition at
the same frequency.

Uhh.. really?

Intel Corporation Intel D875PBZ motherboard (AA-301) (3.4 GHz,
Pentium 4 Processor with HT Technology Extreme Edition)
1548 1561

Seems to me like the Extreme Edition is still a decent amount faster..

The 3.4E result is with HT on and the 3.4 result is with HT off. No
published way, so far as I can tell to sort out the effects of HT on vs.
HT off as compared to 3.4 vs. 3.4E.

Tough call. I wouldn't imagine that it would help much given the
single-threaded nature of SPEC CPU2000, but Intel is now turning HT on
for all of their newest results, so I'm guessing they found some way
to exploit it for a performance gain.

Hmm, I just noticed that they have some results up for their new i925
platform and the 3.6GHz P4E. They posted a rather respectable
1627/1630 for this setup, faster than the 3.4GHz P4EE.

 

[Nick Maclaren]

|>
|> http://public.itrs.net/Files/2003ITRS/Home2003.htm
|> http://www.intel.com/research/silicon/micron.htm
|>
|> Basically, the outlook looks quite good for the next 5+ years.

Having looked at them, there are a lot of discrepancies. While
I know next to nothing about the details of such technologies,
I am fairly good at spotting inconsistencies. Try a few of the
following:

90 nm mass production in 2003? Demonstration versions only; ITRS
correctly claims 2004 for 90 nm. Note that the extra year was from
being able to get the process to produce working CPUs to the point
where they could be produced economically and viably.

Intel are quoting 65 nm for 2005. Well, I have this bridge for
sale .... ITRS quite reasonably talk about 2007. Intel may well
sell their first 65 nm CPUs on the open market in 2006, as they
did with the 90 nm ones in 2003, but that doesn't mean that they
will be in serious production.

I looked at the ITRS lithography section and failed to find passive
leakage as a major issue, though it may have been elsewhere. Note
that it ISN'T just a case of preventing the power from increasing,
but being able to REDUCE it. More compact devices means more of
them in smaller spaces.


Regards,
Nick Maclaren.

 

[Jouni Osmala]

The real question that no one at Intel seems to be

True, it is a bit of an overstatement, but CFP2000 seems to be the
exception rather than the norm. Many other tests have shown little to
no improvement, with a number actually being slower on the Prescott
rather than the Northwood. If all results reflected what we see in
SPEC CPU2000 I don't think people would say much, but as it stands
it's left more than a few people (myself included) wonder just what
the heck all those extra transistors really bought them.

Okay most the extra transitors brought them better performance in
DOOM3.
Unfortunately for the rest of the transistors I don't know and those
extra transistors take more area than the already mentioned
transistors.
http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2149&p=4

Jouni Osmala
Helsinki University of Technology

 

[Tony Hill]

Okay most the extra transitors brought them better performance in
DOOM3.
Unfortunately for the rest of the transistors I don't know and those
extra transistors take more area than the already mentioned
transistors.
http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2149&p=4

On the other hand it's slower than the Extreme Edition, and if Intel
had done a straight shrink of the P4EE down to a 90nm fab process they
probably would have ended up with more or less the same die size as
the P4 "Prescott".

Certainly there are situations where the Prescott does beat the
Northwood, but as mentioned above, there are also many tests that show
no improvement and even a fair number that show the Prescott being
slower. With a more than 100% increase in transistor count one would
normally expect a MUCH more convincing sign of improvement.