Advantages of Parallel Hz

[Guy Macon]

I think it is likely he didn't understand your point. He appears to
be inteligent but ignorant. He didn't know where the leakage current
happened for example.

*willfully* ignorant. I explained to him how to end his ignorance
(buy a ptotoboard and some logic chips and start building things).
He thanked me and continied down his former path (posting wild
theories based on not knowing how things work.)

 

[Guy Macon]

I am Aspergered.

Ah. Many fine engineers are as well. You need to stop doing
what you are doing here. What you are doing here amplifies
your weaknesses (communicating with others). You need to do
as I suggested, get that protoboard, and start building things.
That will amplify your strengths, by causing you to relate to
real circuits rather than imaginary ones.

Seriously. My advice to you is good. You will benefit greatly
by leaving the world of circuits that are thoughts/words and
entering the world of circuits that are silicon/copper.

Guy Macon
<http://www.guymacon.com/>

 

[The little lost angel]

Hardware logic.

If you read the wikipedia links I posted and quoted, you'll find that
there is a real-time, hardware-based alternative to ROM and microcode.

Every regular in CSIPHC knows I'm the village idiot (and now the
ACHH/SED/ SEB/CA folks too), so please explain clearly in simpler
terms about every stage/component of how it's done because I can't
understand how the wiki links to your ideal PC generating say "Canon
in D" without a source.

 

[krw]

On Sun, 06 May 2007 01:08:43 -0700, Radium wrote:
You have yet to ask a serious question.
How does SB16 ISA's FM synth freshly generate its instructions?
SB16 ISA's FM synth doesn't freshly generate its instructions.
It freshly synthesizes (electrical representations of) sounds based on
instructions it receives from the device that owns, and is controlling,
the ISA bus.

Okay. That is what I meant. Sorry for the misunderstanding.

I want my CPU to freshly generate electronic signals [instead of
playing them back from ROM] "based on instructions it receives from
the device that owns, and is controlling" it.

So you want micro code But where do you get the instructions that
control the micro code from?

No microcode.

The PPC-750 is not microcoded. Perhaps you want a G3 Mac, or
Nintendo game console.

Hardware logic.

PPC-750 (or 60x).

If you read the wikipedia links I posted and quoted, you'll find that
there is a real-time, hardware-based alternative to ROM and microcode.

Certqinly there is. I find it hard to believe that a user would
care.

 

[Wilco Dijkstra]

Obviously, I prefer the former over the latter. I like real-time
hardware. I dislike latency and buffering and want the least of them
as possible.

That's reasonable. There exist lots of CPUs that are good at realtime, and
most PCs contain at least 5 realtime CPUs (in the harddrive etc).

In order to have the least amount of latency and
buffering, all parts of the PC must be fully-hardware with as little
software as necessary.

How did you get to that incorrect conclusion? If you implement software in
hardware, you typically have latencies and buffering. Some simple problems
would run faster (say encryption) but most programs would not benefit in any
way from being implemented in hardware. In any case, how would you
implement something like Windows in hardware? CPUs are already complex
enough...

Wilco

 

[Stephen J. Rush]

That's reasonable. There exist lots of CPUs that are good at realtime, and
most PCs contain at least 5 realtime CPUs (in the harddrive etc).


How did you get to that incorrect conclusion? If you implement software in
hardware, you typically have latencies and buffering. Some simple problems
would run faster (say encryption) but most programs would not benefit in any
way from being implemented in hardware. In any case, how would you
implement something like Windows in hardware? CPUs are already complex
enough...

Please don't feed the troll.

 

[Wilco Dijkstra]

On Sun, 06 May 2007 01:08:43 -0700, Radium wrote:
You have yet to ask a serious question.
How does SB16 ISA's FM synth freshly generate its instructions?
SB16 ISA's FM synth doesn't freshly generate its instructions.
It freshly synthesizes (electrical representations of) sounds based on
instructions it receives from the device that owns, and is controlling,
the ISA bus.

Okay. That is what I meant. Sorry for the misunderstanding.

I want my CPU to freshly generate electronic signals [instead of
playing them back from ROM] "based on instructions it receives from
the device that owns, and is controlling" it.

So you want micro code But where do you get the instructions that
control the micro code from?

No microcode.

Well you're in luck then as most CPUs don't have any micro code anymore.
Look up RISC. It would be easier for people to understand you if you used the
correct terms to describe what you want...

Hardware logic.

You should read some books about how CPUs actually work. Instructions are
executed, not generated, by hardware logic. Instructions are ultimately generated
by humans, usually via one or more translation steps.

If you read the wikipedia links I posted and quoted, you'll find that
there is a real-time, hardware-based alternative to ROM and microcode.

You mean RISC? The kind of CPU that you want already exists.

Wilco

 

[kony]

I wish commercial PCs were made that way. Sadly, my wish is way too
good to ever be true.

No you don't, you are spewing idiotic bullshit. What you
continually describe is to take a device that works and
cripple it with random ideas that DON'T WORK.

The modern computer is an evolution of ideas that DO WORK.
If your random nonsense was viable, it WOULD BE ALREADY.

 

[Bob Myers]

Hardware logic.

If you read the wikipedia links I posted and quoted, you'll find that
there is a real-time, hardware-based alternative to ROM and microcode.

And making the completely unwarranted assumption that you have
understood what you read there, perhaps you'd now like to elaborate
on how this approach is (a) functionally distinct from ROM-based
microcode and (b) what its specific advantages (and disadvantages)
might be.

If nothing else, this may be entertaining.

Bob M.

 

[Rich Grise]

Every regular in CSIPHC knows I'm the village idiot (and now the
ACHH/SED/ SEB/CA folks too), so please explain clearly in simpler
terms about every stage/component of how it's done because I can't
understand how the wiki links to your ideal PC generating say "Canon
in D" without a source.

In s.e.d, we don't consider you the village idiot - we've got about a half-
dozen contenders for that spot (some would even say I'm one, but only
because they disagree with my politics ;-) ) - If anything, you're the
oppposite - you ask real questions and pay attention to the answers.
That's considered quite admirable around these here parts
(sci.electronics.design).

Cheers!
Rich

 

[krw]

news:[email protected]...

On May 7, 11:27 am, Rich Grise <[email protected]> wrote:

On May 5, 9:57 pm, "Bob Myers" <[email protected]> wrote:

You have yet to ask a serious question.

How does SB16 ISA's FM synth freshly generate its instructions?

SB16 ISA's FM synth doesn't freshly generate its instructions.

It freshly synthesizes (electrical representations of) sounds based on
instructions it receives from the device that owns, and is controlling,
the ISA bus.

Okay. That is what I meant. Sorry for the misunderstanding.

I want my CPU to freshly generate electronic signals [instead of
playing them back from ROM] "based on instructions it receives from
the device that owns, and is controlling" it.

So you want micro code But where do you get the instructions that
control the micro code from?

No microcode.

Well you're in luck then as most CPUs don't have any micro code anymore.
Look up RISC. It would be easier for people to understand you if you used the
correct terms to describe what you want...

Most modern ones do (have microcode), even RISC processors. For
example, among the PowerPCs, only the 60x and 750s are hard-wired.
Power4 (including PPC-970), and Power 5 are microcoded. Many
instructions translate to one microinstruction but the microcode is
there. Many are cracked into two microinstructions and others have
vertical microcode.

You should read some books about how CPUs actually work. Instructions are
executed, not generated, by hardware logic. Instructions are ultimately generated
by humans, usually via one or more translation steps.

You mean RISC? The kind of CPU that you want already exists.

Not many any more.

 

[Wilco Dijkstra]

On May 7, 12:12 pm, "Wilco Dijkstra" <[email protected]>
wrote:




On Sun, 06 May 2007 01:08:43 -0700, Radium wrote:


You have yet to ask a serious question.

How does SB16 ISA's FM synth freshly generate its instructions?

SB16 ISA's FM synth doesn't freshly generate its instructions.

It freshly synthesizes (electrical representations of) sounds based on
instructions it receives from the device that owns, and is controlling,
the ISA bus.

Okay. That is what I meant. Sorry for the misunderstanding.

I want my CPU to freshly generate electronic signals [instead of
playing them back from ROM] "based on instructions it receives from
the device that owns, and is controlling" it.

So you want micro code But where do you get the instructions that
control the micro code from?

No microcode.

Well you're in luck then as most CPUs don't have any micro code anymore.
Look up RISC. It would be easier for people to understand you if you used the
correct terms to describe what you want...

Most modern ones do (have microcode), even RISC processors. For
example, among the PowerPCs, only the 60x and 750s are hard-wired.
Power4 (including PPC-970), and Power 5 are microcoded. Many
instructions translate to one microinstruction but the microcode is
there. Many are cracked into two microinstructions and others have
vertical microcode.

Most RISCs do not contain microcode - not having any microcode is one of
the criteria of being called RISC! While POWER has complex instructions,
only a few instructions are complex and they are effectively expanded rather
than microcoded. Calling Power4 & 5 microcoded is like calling x86 RISC!

Wilco

 

[daytripper]

On May 7, 12:12 pm, "Wilco Dijkstra" <[email protected]>
wrote:




On Sun, 06 May 2007 01:08:43 -0700, Radium wrote:


You have yet to ask a serious question.

How does SB16 ISA's FM synth freshly generate its instructions?

SB16 ISA's FM synth doesn't freshly generate its instructions.

It freshly synthesizes (electrical representations of) sounds based on
instructions it receives from the device that owns, and is controlling,
the ISA bus.

Okay. That is what I meant. Sorry for the misunderstanding.

I want my CPU to freshly generate electronic signals [instead of
playing them back from ROM] "based on instructions it receives from
the device that owns, and is controlling" it.

So you want micro code But where do you get the instructions that
control the micro code from?

No microcode.

Well you're in luck then as most CPUs don't have any micro code anymore.
Look up RISC. It would be easier for people to understand you if you used the
correct terms to describe what you want...

Most modern ones do (have microcode), even RISC processors. For
example, among the PowerPCs, only the 60x and 750s are hard-wired.
Power4 (including PPC-970), and Power 5 are microcoded. Many
instructions translate to one microinstruction but the microcode is
there. Many are cracked into two microinstructions and others have
vertical microcode.

Most RISCs do not contain microcode - not having any microcode is one of
the criteria of being called RISC! While POWER has complex instructions,
only a few instructions are complex and they are effectively expanded rather
than microcoded. Calling Power4 & 5 microcoded is like calling x86 RISC!

Wilco

Ok then, name one significant processor today that is totally ucode free...

 

[Wilco Dijkstra]

On Tue, 08 May 2007 21:37:15 GMT, "Wilco Dijkstra"

Ok then, name one significant processor today that is totally ucode free...

Every one of the billions of ARM CPUs that are sold every year for example.

Wilco

 

[Rich Grise]

(e-mail address removed) says...

On May 7, 12:12 pm, "Wilco Dijkstra" <[email protected]>
On Sun, 06 May 2007 01:08:43 -0700, Radium wrote:

You have yet to ask a serious question.

How does SB16 ISA's FM synth freshly generate its instructions?

SB16 ISA's FM synth doesn't freshly generate its instructions.

It freshly synthesizes (electrical representations of) sounds based on
instructions it receives from the device that owns, and is controlling,
the ISA bus.

Okay. That is what I meant. Sorry for the misunderstanding.

I want my CPU to freshly generate electronic signals [instead of
playing them back from ROM] "based on instructions it receives from
the device that owns, and is controlling" it.

So you want micro code But where do you get the instructions that
control the micro code from?

No microcode.

Well you're in luck then as most CPUs don't have any micro code anymore.
Look up RISC. It would be easier for people to understand you if you used the
correct terms to describe what you want...

Most modern ones do (have microcode), even RISC processors. For
example, among the PowerPCs, only the 60x and 750s are hard-wired.
Power4 (including PPC-970), and Power 5 are microcoded. Many
instructions translate to one microinstruction but the microcode is
there. Many are cracked into two microinstructions and others have
vertical microcode.

Most RISCs do not contain microcode - not having any microcode is one of
the criteria of being called RISC! While POWER has complex instructions,
only a few instructions are complex and they are effectively expanded rather
than microcoded. Calling Power4 & 5 microcoded is like calling x86 RISC!

The 8008 was kewl - it was as if the machine instructions were, themselves,
microcode. There was an op, a source, and a destination, which iNtel did
backwards, unless they meant MOV A,B to be like LET A=B or something.
Anyway, the instruction register latch was connected right to the source
dest data selector and so on.

Cheers!
Rich

 

[MooseFET]

On May 7, 12:12 pm, "Wilco Dijkstra" <[email protected]>
wrote:

On Sun, 06 May 2007 01:08:43 -0700, Radium wrote:
You have yet to ask a serious question.
How does SB16 ISA's FM synth freshly generate its instructions?
SB16 ISA's FM synth doesn't freshly generate its instructions.
It freshly synthesizes (electrical representations of) sounds based on
instructions it receives from the device that owns, and is controlling,
the ISA bus.
Okay. That is what I meant. Sorry for the misunderstanding.
I want my CPU to freshly generate electronic signals [instead of
playing them back from ROM] "based on instructions it receives from
the device that owns, and is controlling" it.
So you want micro code But where do you get the instructions that
control the micro code from?
No microcode.
Well you're in luck then as most CPUs don't have any micro code anymore.
Look up RISC. It would be easier for people to understand you if you used the
correct terms to describe what you want...

Most modern ones do (have microcode), even RISC processors. For
example, among the PowerPCs, only the 60x and 750s are hard-wired.
Power4 (including PPC-970), and Power 5 are microcoded. Many
instructions translate to one microinstruction but the microcode is
there. Many are cracked into two microinstructions and others have
vertical microcode.

Most RISCs do not contain microcode - not having any microcode is one of
the criteria of being called RISC!

No, the criteria is that the number of instructions be low and the
transistors that would have done the seldom used instructions used to
speed up the common ones. I don't think you would want to call
something like the CDP1802 a RISK. It had no microcode. It had 16,
16 bit registers and a low number of instructions.

 

[krw]

On May 7, 12:12 pm, "Wilco Dijkstra" <[email protected]>
wrote:




On Sun, 06 May 2007 01:08:43 -0700, Radium wrote:


You have yet to ask a serious question.

How does SB16 ISA's FM synth freshly generate its instructions?

SB16 ISA's FM synth doesn't freshly generate its instructions.

It freshly synthesizes (electrical representations of) sounds based on
instructions it receives from the device that owns, and is controlling,
the ISA bus.

Okay. That is what I meant. Sorry for the misunderstanding.

I want my CPU to freshly generate electronic signals [instead of
playing them back from ROM] "based on instructions it receives from
the device that owns, and is controlling" it.

So you want micro code But where do you get the instructions that
control the micro code from?

No microcode.

Well you're in luck then as most CPUs don't have any micro code anymore.
Look up RISC. It would be easier for people to understand you if you used the
correct terms to describe what you want...

Most modern ones do (have microcode), even RISC processors. For
example, among the PowerPCs, only the 60x and 750s are hard-wired.
Power4 (including PPC-970), and Power 5 are microcoded. Many
instructions translate to one microinstruction but the microcode is
there. Many are cracked into two microinstructions and others have
vertical microcode.

Most RISCs do not contain microcode - not having any microcode is one of
the criteria of being called RISC!

No, "RISC" does not mean no microcode. RISC == simple instructions,
for example, no arithmetic on memory instructions.

While POWER has complex instructions,

No, it has no "complex" instructions. There are no read-operate,
write-operate, or any such combination. Each instruction is quite
simple.

only a few instructions are complex and they are effectively expanded rather
than microcoded. Calling Power4 & 5 microcoded is like calling x86 RISC!

Sorry, but The Power4 and 5 certainly are microcoded.

 

[krw]

On May 7, 12:12 pm, "Wilco Dijkstra" <[email protected]>
wrote:

On May 7, 11:27 am, Rich Grise <[email protected]> wrote:

On May 5, 9:57 pm, "Bob Myers" <[email protected]> wrote:

You have yet to ask a serious question.

How does SB16 ISA's FM synth freshly generate its instructions?

SB16 ISA's FM synth doesn't freshly generate its instructions.

It freshly synthesizes (electrical representations of) sounds based on
instructions it receives from the device that owns, and is controlling,
the ISA bus.

Okay. That is what I meant. Sorry for the misunderstanding.

I want my CPU to freshly generate electronic signals [instead of
playing them back from ROM] "based on instructions it receives from
the device that owns, and is controlling" it.

So you want micro code But where do you get the instructions that
control the micro code from?

No microcode.

Well you're in luck then as most CPUs don't have any micro code anymore.
Look up RISC. It would be easier for people to understand you if you used the
correct terms to describe what you want...

Most modern ones do (have microcode), even RISC processors. For
example, among the PowerPCs, only the 60x and 750s are hard-wired.
Power4 (including PPC-970), and Power 5 are microcoded. Many
instructions translate to one microinstruction but the microcode is
there. Many are cracked into two microinstructions and others have
vertical microcode.

Most RISCs do not contain microcode - not having any microcode is one of
the criteria of being called RISC!

No, the criteria is that the number of instructions be low

No, the number of instructions has nothing to do with RISC/CISC.
PowerPC has as many instructions as x86. Depending on how you count
them, more.

and the
transistors that would have done the seldom used instructions used to
speed up the common ones.

That's not a definition, rather a motivation.

I don't think you would want to call
something like the CDP1802 a RISK. It had no microcode. It had 16,
16 bit registers and a low number of instructions.

Seems to fit your definition?

 

[krw]

And making the completely unwarranted assumption that you have
understood what you read there, perhaps you'd now like to elaborate
on how this approach is (a) functionally distinct from ROM-based
microcode and (b) what its specific advantages (and disadvantages)
might be.

Particularly when said "ROM" is called a "PLA" and is in reality
synthesized logic. ;-)

If nothing else, this may be entertaining.

Radium says he has Asberger's, so there may not be much entertainment
to see here.

 

[Wilco Dijkstra]

No, "RISC" does not mean no microcode. RISC == simple instructions,
for example, no arithmetic on memory instructions.

Simple instructions in the architecture implies no microcode in the implementation.

No, it has no "complex" instructions. There are no read-operate,
write-operate, or any such combination. Each instruction is quite
simple.

Complex is a relative term. POWER, unlike most other RISCs, has quite a few
complex instructions that take more than 1 cycle, do more than 1 memory access
or have more than 2 input and 1 destination register (all RISC criteria). Examples
are multiple load/store, load/store with base update, unaligned load/store, string
instructions, and so on...

Alpha is an example of a pure RISC that only supports simple instructions.

Sorry, but The Power4 and 5 certainly are microcoded.

They most definitely are not. You're confusing the out of order execution engine
with a micro code engine. These are completely different beasts.

Wilco