1GB page tables and 48-bit physical addressing!

[YKhan]

AMD readies hounds to blood Intel's next gen hares
"The HPC crowd will also love the memory controller enhancements. Think
1GB page tables and 48-bit physical addressing for a total of 256TB of
RAM. Can you say Cray and SGI doing the happy dance? This part should
have a happy home in large servers."
http://www.theinquirer.net/?article=30042

Also doubling the floating point units as was mentioned previously. It
appears to be twice the number or 64-bit fpus, rather than an increase
from a 64-bit to a 128-bit fpu.

Yousuf Khan

 

[Tony Hill]

AMD readies hounds to blood Intel's next gen hares
"The HPC crowd will also love the memory controller enhancements. Think
1GB page tables and 48-bit physical addressing for a total of 256TB of
RAM. Can you say Cray and SGI doing the happy dance? This part should
have a happy home in large servers."
http://www.theinquirer.net/?article=30042

I suppose this is a good idea going forward, but I'm not sure that
either Cray or SGI are doing too many happy dances. The maximum
memory controllers AMD chips can address natively is 8. Each chip can
hold up to 8 DIMMs. Currently they max out at 4GB per DIMM. So the
grand total of physical memory they can address is 256GB... and I've
never seen anyone build such a configuration (128GB is the most I've
seen).

Beyond 8 CPUs, ie what the HPC community is going to use, they have to
go beyond what can be natively addressed by the processor. Then we're
dealing with the virtual memory addressing, where it's already at
48-bits/256TB.

Also doubling the floating point units as was mentioned previously. It
appears to be twice the number or 64-bit fpus, rather than an increase
from a 64-bit to a 128-bit fpu.

More to the point, we're probably talking about doubling SSE units
here.

 

[Yousuf Khan]

Beyond 8 CPUs, ie what the HPC community is going to use, they have to
go beyond what can be natively addressed by the processor. Then we're
dealing with the virtual memory addressing, where it's already at
48-bits/256TB.

Well, obviously the virtual memory limits will go up too. The current
48-bit virtual limit is based on 1MB pages. With a 1GB page, we're
probably talking about a 56-bit virtual limit now.

Yousuf Khan

 

[nobody]

AMD readies hounds to blood Intel's next gen hares
"The HPC crowd will also love the memory controller enhancements. Think
1GB page tables and 48-bit physical addressing for a total of 256TB of
RAM. Can you say Cray and SGI doing the happy dance? This part should
have a happy home in large servers."
http://www.theinquirer.net/?article=30042

Also doubling the floating point units as was mentioned previously. It
appears to be twice the number or 64-bit fpus, rather than an increase
from a 64-bit to a 128-bit fpu.

Yousuf Khan

Deerhound... Wolfhound... Whatever other hounds - all names
dog-related or, scientifically speaking, canine. Could that be a hint
to K-9?
;-)

NNN

 

[YKhan]

Deerhound... Wolfhound... Whatever other hounds - all names
dog-related or, scientifically speaking, canine. Could that be a hint
to K-9?

I think AMD has been dreading the day that they would need to create
the K-9 processor since their first K-5 processor.

Yousuf Khan

 

[nobody]

Deerhound... Wolfhound... Whatever other hounds - all names
dog-related or, scientifically speaking, canine. Could that be a hint
to K-9?

I think AMD has been dreading the day that they would need to create
the K-9 processor since their first K-5 processor.

Yousuf Khan

Why? It would only underscore the jorney AMD made from being a
perrenial _underdog_ to becoming the _top dog_ (at least,
performance-wise).

NNN

 

[Lee Waun]

Deerhound... Wolfhound... Whatever other hounds - all names
dog-related or, scientifically speaking, canine. Could that be a hint
to K-9?

I think AMD has been dreading the day that they would need to create
the K-9 processor since their first K-5 processor.

Yousuf Khan

Does that mean they know the K9 will be a dog of a processor?