What core speed were/are north bridges and/or MCH's clocked at?

[jack]

: Um, nothing writes to memory unless the CPU initiates it. DMA
: xfers are not initiated without CPU intervention (at least to
: set up the starting and ending addresses). I'm referring here
: to a single CPU situation w/a N. Bridge.

1. You are top posting....learn how to communicate in Usenet or get the
f**k off this channel!

2. You're actually going to argue with Daytrip?? AH
HAHAHAHAHAHAHAHAHAHA!!!!

3. Get a clue....

j.

 

[David Kanter]

: Um, nothing writes to memory unless the CPU initiates it. DMA
: xfers are not initiated without CPU intervention (at least to
: set up the starting and ending addresses). I'm referring here
: to a single CPU situation w/a N. Bridge.

1. You are top posting....learn how to communicate in Usenet or get the
f**k off this channel!

2. You're actually going to argue with Daytrip?? AH
HAHAHAHAHAHAHAHAHAHA!!!!

Who is day tripper? Why is he such an authority? I recognize that
most of his answers are cogent and on point (in this thread at least),
but i don't see him as a figure to be revered as handing out the word
on MPU or chipset design.

DK

 

[daytripper]

Who is day tripper? Why is he such an authority? I recognize that
most of his answers are cogent and on point (in this thread at least),
but i don't see him as a figure to be revered as handing out the word
on MPU or chipset design.

DK

fwiw, I've never sought such a position...

/daytripper (...it sounds too much like actual work ;-)

 

[Ken.Janik]

most of his answers are cogent and on point (in this thread at least),
but i don't see him as a figure to be revered as handing out the word
on MPU or chipset design.

DK

Just don't question his fishing expertise. ;-)
- Ken

 

[krw]

Um, nothing writes to memory unless the CPU initiates it. DMA xfers are not
initiated without CPU intervention (at least to set up the starting and
ending addresses). I'm referring here to a single CPU situation w/a N.
Bridge.

Nothing? You really need to be beat about the head and body by a
*large* cluestick!


BTW, you have been but the hurt apparently hasn't set in yet.

 

[krw]

Who is day tripper? Why is he such an authority? I recognize that
most of his answers are cogent and on point (in this thread at least),
but i don't see him as a figure to be revered as handing out the word
on MPU or chipset design.

Who the **** are you? A DeanK clone? The rest here pretty much
know who 'tripper is. ...some better than others. To quote your
boss, what a maroon!

 

[David Kanter]

Who the **** are you?

I think it's pretty easy to find that out if you know how to use a
search engine. One could ask the same of you...and there Google is
somewhat less helpful.

A DeanK clone? The rest here pretty much
know who 'tripper is.

That's truly wonderful, why don't you give yourself a pat on the back.
I don't, in case you missed that particular implication.

Nor am I inclined to accept some random anonymous person as an expert
in the field unless I am familiar with the work they have done and
their areas of expertise. Anyone can claim to know something about
chipsets or MPUs, but how many of those folks have taped one out...or
taped out a relevant product. Working on an embedded design does not
necessarily mean you know about high performance design on bleeding
edge process technology, just as experience designing high performance
MPUs does not imply knowledge about tweaks for low power and efficient
operation.

DK

 

[krw]

I think it's pretty easy to find that out if you know how to use a
search engine. One could ask the same of you...and there Google is
somewhat less helpful.

That's truly wonderful, why don't you give yourself a pat on the back.
I don't, in case you missed that particular implication.

He's de-cloaked here in .chips at least once. Maybe you should pay
closer attention.

Nor am I inclined to accept some random anonymous person as an expert
in the field unless I am familiar with the work they have done and
their areas of expertise. Anyone can claim to know something about
chipsets or MPUs, but how many of those folks have taped one out...or
taped out a relevant product. Working on an embedded design does not
necessarily mean you know about high performance design on bleeding
edge process technology, just as experience designing high performance
MPUs does not imply knowledge about tweaks for low power and efficient
operation.

There is a lot more to this biz than "taping out" an MPU. Perhaps
you should pay attention to what 'triper says.

DK

DK == Dean Kent?

 

[daytripper]

He's de-cloaked here in .chips at least once. Maybe you should pay
closer attention.


There is a lot more to this biz than "taping out" an MPU. Perhaps
you should pay attention to what 'triper says.


DK == Dean Kent?

Easy there, youngster ;-) It's a beautiful day today, let's not spoil it


Let us return to the question at hand - which I believe started with a claim
by "pigdos" that on systems sporting a north bridge the front side bus address
lines are "unidirectional" - from processor to bridge.

After making said claim, pigdos ran right through the stop sign labeled "cache
coherency" that was erected by Mr. Kanter (and supported by myownself).

pigdos' *reply* was "In a northbridge design the address lines would run one
way -- from the CPU to the N. Bridge."

When again challenged, he responded "Um, nothing writes to memory unless the
CPU initiates it. DMA xfers are not initiated without CPU intervention (at
least to set up the starting and ending addresses). I'm referring here to a
single CPU situation w/a N. Bridge."

Umm...Okay, so stipulated. Doesn't change a thing, of course.

Bottom line: I don't think pigdos understands the ramifications of processor
memory caches and IO devices that can initiate memory transactions.

I also don't think he knows about MSI....And what *that* means wrt fsb
transactions.

Thus, my conclusion stands: pigdos needs to do a LOT of homework before he
could even hope to hold up his end of the discussion.

/daytripper
(Of course, if he *did* the homework, that'd be the end of the discussion ;-)

 

[krw]

Easy there, youngster ;-) It's a beautiful day today, let's not spoil it

It's been a *long* time since anyone called me "youngster"! ;-)

 

[daytripper]

It's been a *long* time since anyone called me "youngster"! ;-)

Merry Christmas

/daytripper (can't say I didn't give you anything ;-)

 

[David Kanter]

...and I trust everything on the net? <guffaw>

Its reasonably easy to establish who I am...in fact, some of the folks
at IBM have met me (and quite a few who used to work there).

He's de-cloaked here in .chips at least once. Maybe you should pay
closer attention.

Could be, but I don't follow every thread religiously, nor do I really

There is a lot more to this biz than "taping out" an MPU. Perhaps
you should pay attention to what 'triper says.

DK == Dean Kent?

David Kanter. It's just a rather messy coincidence that Dean and I
have the same initials and each own half of real world tech.

DK

 

[David Kanter]

Easy there, youngster ;-) It's a beautiful day today, let's not spoil it

Let us return to the question at hand - which I believe started with a claim
by "pigdos" that on systems sporting a north bridge the front side bus address
lines are "unidirectional" - from processor to bridge.

After making said claim, pigdos ran right through the stop sign labeled "cache
coherency" that was erected by Mr. Kanter (and supported by myownself).

pigdos' *reply* was "In a northbridge design the address lines would run one
way -- from the CPU to the N. Bridge."

When again challenged, he responded "Um, nothing writes to memory unless the
CPU initiates it. DMA xfers are not initiated without CPU intervention (at
least to set up the starting and ending addresses). I'm referring here to a
single CPU situation w/a N. Bridge."

Umm...Okay, so stipulated. Doesn't change a thing, of course.

Bottom line: I don't think pigdos understands the ramifications of processor
memory caches and IO devices that can initiate memory transactions.

I also don't think he knows about MSI....And what *that* means wrt fsb
transactions.

Thus, my conclusion stands: pigdos needs to do a LOT of homework before he
could even hope to hold up his end of the discussion.

Indeed, I think everyone could agree to that.

Even getting back to his main point (what frequency does the chipset
run at internally), he needs to really rethink what is necessary. Now
that he knows that as a rough approximation, the NB runs at the speed
of the addressing pins on the FSB...he should try and figure out how
that can work and why it is done that way.

DK

 

[George Macdonald]

Who the **** are you? A DeanK clone?

Hummm, been wondering about that myself... DK??... and the err, style is
so-o-o similar.

The rest here pretty much
know who 'tripper is. ...some better than others. To quote your
boss, what a maroon!

I guess this is one umm, "designer" he doesn't talk to regularly.Ô_õ

 

[George Macdonald]

Who is day tripper? Why is he such an authority? I recognize that
most of his answers are cogent and on point (in this thread at least),
but i don't see him as a figure to be revered as handing out the word
on MPU or chipset design.

Who the hell are you to want to know *who* people are and who appointed to
you to interrogation duties?... mark of the true Usenet dilettante-dabbler
that! Trying to figure if you need him on your list of people you "talk"
to?

 

[George Macdonald]

Intel's Blackford MCH chipset, for example, has a "core clock" (aka ""BCLK")
of either 250, 266, or 333 mhz, depending on FSB "speed" (1000, 1066 or
1333mhz, respectively).

No internal multiplier? Then I'm missing something here, unless there's
128-bit or dual 64-bit paths internally, it doesn't seem to jibe that data
is arriving and leaving at 6.4GB/s but is clocked internally at 200MHz.
Even so, it doesn't seem to make sense to clock FSB addresses at 400MT/s
(again for a 200MHz BCLK) and then use a 200MHz clock for the internal
logic.

 

[daytripper]

Who the hell are you to want to know *who* people are and who appointed to
you to interrogation duties?... mark of the true Usenet dilettante-dabbler
that! Trying to figure if you need him on your list of people you "talk"
to?

"Feel the love" ;-)

I think it's fine if someone has questions that affect their perception of
things being said. And I'm sure a modicum of Googling would reveal more than
enough old tape on the matter, so I'll spare everyone the suffering ;-)

Cheers

/daytripper
('sides, it's just too beautiful a day today, even with the rain here

 

[krw]

Merry Christmas

....and it's not even Thanksgiving.

/daytripper (can't say I didn't give you anything ;-)

I feel so full of joy, I could skip! ;-)

 

[krw]

Its reasonably easy to establish who I am...in fact, some of the folks
at IBM have met me (and quite a few who used to work there).

Well, aren't you just so special! IBM?! Who wudda guessed.

Could be, but I don't follow every thread religiously, nor do I really

You are a simple pimple. You are like glue to this NG. It's your
reason for living!

David Kanter. It's just a rather messy coincidence that Dean and I
have the same initials and each own half of real world tech.

Messy coincidence? Perhaps. Seems more like a contagion though.

 

[George Macdonald]

"Feel the love" ;-)

I think it's fine if someone has questions that affect their perception of
things being said. And I'm sure a modicum of Googling would reveal more than
enough old tape on the matter, so I'll spare everyone the suffering ;-)

Yeah ok, and may all your pelagic daytrips be fru... umm, fishful?