Re: Gaming AMD vs Intel

Discussion in 'AMD 64 Bit' started by YKhan, Sep 6, 2005.

  1. YKhan

    YKhan Guest

    wrote:
    > So I am wanting to get a new system later this fall. I have read other
    > reviews saying Intel is the way to go for gaming.


    Those reviews must be several years old now. AMD has been tightening
    its hold on the gaming market steady for the past 2-3 years now,
    basically since the Athlon 64 first came out. Prior to that there was a
    period of time (about 6 years ago to 4 years ago) when Intel and AMD
    were trading top spot almost on a weekly basis. Then for a period of
    one year, from about 4 years ago to about 3 years ago, Intel had the
    crown for itself for about a year, as AMD dropped out to concentrate on
    getting the Athlon 64 out.

    Now, it's possible that AMD and Intel will switch positions once again
    in this field, like they have in the past. But there's some evidence
    that AMD will have this crown for several more years still. In the
    transition from the Athlon XP to the Athlon 64, AMD took the time to
    not only improve the design of chips, but it actually redesign some
    very basic concepts of its chips. One example is that the ubiquitous
    front-side bus (FSB), namely AMD got rid of it! The FSB was the method
    by which PC chips had connected to their peripheral devices and its
    memory ever since the first 8088 IBM PC-XT. AMD threw out the FSB, and
    replaced it with two seperate connections, one for the memory and one
    for the peripherals. Intel isn't expected to have a similar system till
    at least 2007; and it's not likely that AMD will remain stagnant
    waiting for Intel to catch up during that time.

    > I am looking for the best performance in games and for burning dvds/cds
    > and web browsing. But the high intensity graphics will be from games
    > like Doom 3.


    None of those tasks are all that demanding for today's generation of
    processors.

    > I don't want a system that will choke on the graphics. I was thiking
    > about the nvidia latest pci-e card.
    >
    > Any thoughts on intel vs AMD?


    Well, you touched on one thing that is very important these days: the
    graphics card. The performance war at the CPU level has sort of taken a
    backseat to the war of the video cards for gaming. It's not so much
    Intel vs. AMD as it is Nvidia vs. ATI.

    That being said, AMD does offer some interesting advantages to aid your
    choice of video cards. These days video cards have gotten into a
    dual-core battle of their own, ATI offers its Crossfire technology,
    while Nvidia offers its SLI technology. Due to the seperated memory and
    peripheral connection paths that AMD offers in Athlon 64 these days,
    both Crossfire and SLI work much better under an AMD processor than in
    an Intel processor. I think the numbers they have come up with
    generally show that a Crossfire or SLI system will show a 40%
    improvement under Intel, but an 80% improvement under AMD.

    And that's not all, although this is something that's for the future,
    and won't affect any processor purchase that you make today, there was
    a rumour that AMD has decided to integrate a PCI-e interface directly
    into the processor, which would offer even higher performance for SLI
    or Crossfire. But that's something probably two years out too.

    Yousuf Khan
     
    YKhan, Sep 6, 2005
    #1
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  2. YKhan

    Guest

    On 5 Sep 2005 16:22:51 -0700, "YKhan" <> wrote:

    > wrote:

    ....snip...
    >
    >> I am looking for the best performance in games and for burning dvds/cds
    >> and web browsing. But the high intensity graphics will be from games
    >> like Doom 3.

    >
    >None of those tasks are all that demanding for today's generation of
    >processors.
    >

    Maybe straight copying is not demanding. Bur burning DVDs from .avi
    files is (unless NeroVision Express 3 is a piece of crap, which IMO
    it's not). When it does encoding, both of my (admittedly not-so-new)
    Opterons 242 are loaded above 90%, and graphics card takes no part of
    the job.

    >> I don't want a system that will choke on the graphics. I was thiking
    >> about the nvidia latest pci-e card.
    >>
    >> Any thoughts on intel vs AMD?

    >
    >Well, you touched on one thing that is very important these days: the
    >graphics card. The performance war at the CPU level has sort of taken a
    >backseat to the war of the video cards for gaming. It's not so much
    >Intel vs. AMD as it is Nvidia vs. ATI.
    >
    >That being said, AMD does offer some interesting advantages to aid your
    >choice of video cards. These days video cards have gotten into a
    >dual-core battle of their own, ATI offers its Crossfire technology,
    >while Nvidia offers its SLI technology. Due to the seperated memory and
    >peripheral connection paths that AMD offers in Athlon 64 these days,
    >both Crossfire and SLI work much better under an AMD processor than in
    >an Intel processor. I think the numbers they have come up with
    >generally show that a Crossfire or SLI system will show a 40%
    >improvement under Intel, but an 80% improvement under AMD.
    >
    >And that's not all, although this is something that's for the future,
    >and won't affect any processor purchase that you make today, there was
    >a rumour that AMD has decided to integrate a PCI-e interface directly
    >into the processor, which would offer even higher performance for SLI
    >or Crossfire. But that's something probably two years out too.
    >
    > Yousuf Khan


    Agree with all said here about the advantages of A64. So much so that
    I'd advice to multiply it by 2. Even though the fastest A64 X2 has a
    notch slower clock than the fastest single core, it gets ahead if you
    are multitasking. Or, if your pockets allow for it, go for dual
    dual-core Opteron, making it a quad. Maybe today's games can't take
    real advantage of multithreading, but I bet the games of tomorrow (and
    not only games) are already being coded to use multiple cores to their
    advantage.

    NNN
     
    , Sep 6, 2005
    #2
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  3. YKhan

    Wes Newell Guest

    On Mon, 05 Sep 2005 16:22:51 -0700, YKhan wrote:

    > not only improve the design of chips, but it actually redesign some
    > very basic concepts of its chips. One example is that the ubiquitous
    > front-side bus (FSB), namely AMD got rid of it! The FSB was the method
    > by which PC chips had connected to their peripheral devices and its
    > memory ever since the first 8088 IBM PC-XT. AMD threw out the FSB, and
    > replaced it with two seperate connections, one for the memory and one
    > for the peripherals.


    For clearity, AMD didn't get rid of the FSB, they just stopped calling it
    a FSB, even though that's what it still is, by definition. They did
    however move the memory controller onto the cpu, so that ram data now has
    it's own data path to the CPU. This move, and not the move to an HT link
    for the FSB is where the major performance gain was made. With the move to
    the seperate memory bus, the FSB (now a serial HT link, instead of a
    paralell bus) speed is of little importance.

    --
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    Wes Newell, Sep 6, 2005
    #3
  4. On Tue, 06 Sep 2005 06:14:02 GMT, Wes Newell <>
    wrote:

    >On Mon, 05 Sep 2005 16:22:51 -0700, YKhan wrote:
    >
    >> not only improve the design of chips, but it actually redesign some
    >> very basic concepts of its chips. One example is that the ubiquitous
    >> front-side bus (FSB), namely AMD got rid of it! The FSB was the method
    >> by which PC chips had connected to their peripheral devices and its
    >> memory ever since the first 8088 IBM PC-XT. AMD threw out the FSB, and
    >> replaced it with two seperate connections, one for the memory and one
    >> for the peripherals.

    >
    >For clearity, AMD didn't get rid of the FSB, they just stopped calling it
    >a FSB, even though that's what it still is, by definition.


    The term FSB came about with Intel's Pentium Pro, where the dual chip
    CPU/L2 cache package contained a BSB (Back Side Bus) connection between the
    CPU chip and L2 cache chip. Until then the CPU system bus had carried CPU
    <-> L2 cache data as well as I/O and memory transfers. By definition, a
    FSB carried all CPU<->memory and CPU<->I/O transfers... but not CPU<->L2
    cache transfers. To me calling AMD's HT a FSB is about as valid as
    continuing to use North Bridge & South Bridge for the two chips normally
    used in a chipset - it's not really applicable any more but people will say
    it as a convenience term

    > They did
    >however move the memory controller onto the cpu, so that ram data now has
    >it's own data path to the CPU. This move, and not the move to an HT link
    >for the FSB is where the major performance gain was made. With the move to
    >the seperate memory bus, the FSB (now a serial HT link, instead of a
    >paralell bus) speed is of little importance.


    As recently discussed here, HyperTransport is not a serial bus - it *is*
    packetized and it is point-to-point/uni-directional but each byte-width
    path has a separate clock signal and the chip/system designers have to pay
    close attention to clock skew.

    As far as speed, with current Athlon64 systems, the 2-byte-wide down-link
    from CPU->chipset->PCI-e(x16) is, in theory, maxed out at the 1GHz clock
    rate. Put another way, the current PCI-e x16 graphics path has a max
    bandwidth of 4.1GB/s; the HT down-link has a max bandwidth of 4GB/s so in
    theory, at least, it would be possible for memory->graphics transfers to
    saturate the HT down-link.

    I don't think this is a problem for the moment but add in that the 4GB/s HT
    up-link for an integrated graphics chipset could be seriously stressed and
    cause HT traffic contention, it could lead to problems down the road... as
    well as supply ammo to anti-AMD marketing efforts. So yes, speed of HT is
    an issue and the integrated PCI-e that AMD is adding will help mitigate
    those err, concerns.

    --
    Rgds, George Macdonald
     
    George Macdonald, Sep 6, 2005
    #4
  5. YKhan

    Guest

    >Or, if your pockets allow for it, go for dual
    >dual-core Opteron, making it a quad. Maybe today's games can't take
    >real advantage of multithreading, but I bet the games of tomorrow (and
    >not only games) are already being coded to use multiple cores to their
    >advantage.


    Forgive me, I have not read much about Opteron chips. Are you saying
    a system with dual 64 bit Opteron chips is about the same as what a
    QUAD A64 X2 would be ?
     
    , Sep 6, 2005
    #5
  6. YKhan

    YKhan Guest

    wrote:
    > >Or, if your pockets allow for it, go for dual
    > >dual-core Opteron, making it a quad. Maybe today's games can't take
    > >real advantage of multithreading, but I bet the games of tomorrow (and
    > >not only games) are already being coded to use multiple cores to their
    > >advantage.

    >
    > Forgive me, I have not read much about Opteron chips. Are you saying
    > a system with dual 64 bit Opteron chips is about the same as what a
    > QUAD A64 X2 would be ?


    No, A64 systems are limited to one and only one CPU socket. So if you
    have a dual-core A64, then that's all you're ever going to get: two
    cores. However, Opteron workstations often have dual sockets, and
    dual-core Opterons in each socket will mean that you have upto four
    cores.

    Yousuf Khan
     
    YKhan, Sep 6, 2005
    #6
  7. YKhan

    YKhan Guest

    To me, a bus would be a multi-drop access medium, with multiple devices
    (including CPUs) all sharing a single data path between each other.
    Hypertransport is a point-to-point interface, you can only connect to
    one other device with each HT link. This would be much the same as old
    collision-based Ethernet vs. switched Ethernet.

    Yousuf Khan
     
    YKhan, Sep 6, 2005
    #7
  8. YKhan

    Wes Newell Guest

    On Tue, 06 Sep 2005 06:09:35 -0400, George Macdonald wrote:

    >>For clearity, AMD didn't get rid of the FSB, they just stopped calling it
    >>a FSB, even though that's what it still is, by definition.

    >
    > The term FSB came about with Intel's Pentium Pro, where the dual chip
    > CPU/L2 cache package contained a BSB (Back Side Bus) connection between the
    > CPU chip and L2 cache chip. Until then the CPU system bus had carried CPU
    > <-> L2 cache data as well as I/O and memory transfers. By definition, a
    > FSB carried all CPU<->memory and CPU<->I/O transfers... but not CPU<->L2
    > cache transfers. To me calling AMD's HT a FSB is about as valid as
    > continuing to use North Bridge & South Bridge for the two chips normally
    > used in a chipset - it's not really applicable any more but people will say
    > it as a convenience term
    >

    FSB by definition connects the CPU to the chipset. HT link by definition
    is just that, any bus using HT technolog and is not limited to
    connections between a cpu and a chipset. So given the choice of
    calling the bus a FSB, or the HT link, FSB fits the bill while HT link
    only describes the type of bus, not the bus itself. IOW's using the term
    FSB specifically refers to the connection between the CPU and chipset,
    while using the term HT link could be any of many different type of
    connections an HT link is used for since it's used in many more
    applications than just a FSB. Some refer to the bus as a system bus, but
    that's generic in nature and could even refer to the memory bus since it's
    a part of the system. So, imo, the bus conncetion between the cpu and
    chipset is still a FSB, thus specifically stating what the two ends
    actually connect to. Simply calling it an HT link doesn't descibe any
    particular bus, and shouldn't be assumed that it means a conncetion
    between a xpu and its chipset, as HT links are currently being used for
    other purposes. Be it convenient or not, it's still there.

    >> They did
    >>however move the memory controller onto the cpu, so that ram data now has
    >>it's own data path to the CPU. This move, and not the move to an HT link
    >>for the FSB is where the major performance gain was made. With the move to
    >>the seperate memory bus, the FSB (now a serial HT link, instead of a
    >>paralell bus) speed is of little importance.

    >
    > As recently discussed here, HyperTransport is not a serial bus - it *is*
    > packetized and it is point-to-point/uni-directional but each byte-width
    > path has a separate clock signal and the chip/system designers have to pay
    > close attention to clock skew.
    >

    I'll go with you on this. Probably a paralell packet network would
    describe it better.

    --
    KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
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    Wes Newell, Sep 6, 2005
    #8
  9. YKhan

    keith Guest

    On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:

    > On Tue, 06 Sep 2005 06:09:35 -0400, George Macdonald wrote:
    >
    >>>For clearity, AMD didn't get rid of the FSB, they just stopped calling it
    >>>a FSB, even though that's what it still is, by definition.

    >>
    >> The term FSB came about with Intel's Pentium Pro, where the dual chip
    >> CPU/L2 cache package contained a BSB (Back Side Bus) connection between the
    >> CPU chip and L2 cache chip. Until then the CPU system bus had carried CPU
    >> <-> L2 cache data as well as I/O and memory transfers. By definition, a
    >> FSB carried all CPU<->memory and CPU<->I/O transfers... but not CPU<->L2
    >> cache transfers. To me calling AMD's HT a FSB is about as valid as
    >> continuing to use North Bridge & South Bridge for the two chips normally
    >> used in a chipset - it's not really applicable any more but people will say
    >> it as a convenience term
    >>

    > FSB by definition connects the CPU to the chipset.


    Nope. As George stated, it was in opposition the "back-side <cache> bus"
    of the P6. The P5 had no "FSB".

    > HT link by definition
    > is just that, any bus using HT technolog and is not limited to
    > connections between a cpu and a chipset.


    Only in your mind. It is in no way an "FSB", since the term is now
    meaningless. The memory bus is elsewhere, so if there *IS* an "FSB" it's
    the memory bus(ses), not the HT channel. The caches are on the
    "back-side" of the memory interface, not other procesors or I/O.

    > So given the choice of calling
    > the bus a FSB, or the HT link, FSB fits the bill while HT link only
    > describes the type of bus, not the bus itself.


    FSB doesn't describe it's function at all. What's the "back side" of the
    HT link?

    > IOW's using the term FSB
    > specifically refers to the connection between the CPU and chipset,


    No, it doesn't. I specifically refers to the fact that the caches are on
    the other side (back side) of the P6 memory bus. That architecture was
    around for a while, so it stuck. There was no "FSB" in the P5
    architecture. It's an invention of the P6 and should stay there, since it
    no longer describes any function.


    > while
    > using the term HT link could be any of many different type of
    > connections an HT link is used for since it's used in many more
    > applications than just a FSB. Some refer to the bus as a system bus,


    "System bus" works for me. I/O bus makes more sense.

    > but
    > that's generic in nature and could even refer to the memory bus since
    > it's a part of the system.


    Since it is the intervace from the processor to the "system", it still
    makes sense. "FSB" makes *no* sense, since it's not on the "front" side
    of anything.

    > So, imo, the bus conncetion between the cpu
    > and chipset is still a FSB, thus specifically stating what the two ends
    > actually connect to. Simply calling it an HT link doesn't descibe any
    > particular bus, and shouldn't be assumed that it means a conncetion
    > between a xpu and its chipset, as HT links are currently being used for
    > other purposes. Be it convenient or not, it's still there.


    Your opinion and $2 may be useful in a Starbuck's. They don't much care
    if you're wrong, as long as you have $2.

    >>> They did
    >>>however move the memory controller onto the cpu, so that ram data now
    >>>has it's own data path to the CPU. This move, and not the move to an HT
    >>>link for the FSB is where the major performance gain was made. With the
    >>>move to the seperate memory bus, the FSB (now a serial HT link, instead
    >>>of a paralell bus) speed is of little importance.

    >>
    >> As recently discussed here, HyperTransport is not a serial bus - it
    >> *is* packetized and it is point-to-point/uni-directional but each
    >> byte-width path has a separate clock signal and the chip/system
    >> designers have to pay close attention to clock skew.
    >>

    > I'll go with you on this. Probably a paralell packet network would
    > describe it better.


    Whatever, but it is *NOT* an "FSB". AMD has broken out of that system
    architecture. ...much like Intel broke into it by moving the L2 traffic
    to the *BACK-SIDE* bus.

    --
    Keith
     
    keith, Sep 7, 2005
    #9
  10. YKhan

    Yousuf Khan Guest

    keith wrote:
    > Nope. As George stated, it was in opposition the "back-side <cache> bus"
    > of the P6. The P5 had no "FSB".


    Maybe in those days it was better known as the "local bus".

    Yousuf Khan
     
    Yousuf Khan, Sep 7, 2005
    #10
  11. YKhan

    Wes Newell Guest

    On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:

    > On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:
    >
    >> FSB by definition connects the CPU to the chipset.

    >
    > Nope. As George stated, it was in opposition the "back-side <cache> bus"
    > of the P6. The P5 had no "FSB".
    >

    Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let's
    see just how many people you can convince of that.:)

    While the term may have originated the way you say, it was then later used
    to indicate the connection between the CPU and the chipset. Now, that same
    connection is the HT link of the K8. So it only makes sense to use the
    same terminology for the very specific connection even though memory data
    now has own single use bus for the memory. The FSB still carries all other
    IO operations to/from the system. Once they move all this into the CPU,
    there will no longer be a FSB. Until then, a duck by any other name is
    still a duck.

    >> HT link by definition is just that, any bus using HT technolog and
    >> is not limited to connections between a cpu and a chipset.

    >
    > Only in your mind. It is in no way an "FSB", since the term is now
    > meaningless. The memory bus is elsewhere, so if there *IS* an "FSB"
    > it's the memory bus(ses), not the HT channel. The caches are on the
    > "back-side" of the memory interface, not other procesors or I/O.
    >

    And I thought only the government could take something so simple and
    fiubar.

    >> So given the choice of calling
    >> the bus a FSB, or the HT link, FSB fits the bill while HT link only
    >> describes the type of bus, not the bus itself.

    >
    > FSB doesn't describe it's function at all. What's the "back side" of
    > the HT link?
    >

    What HT link? Ht links are used everywhere. AFAIK, they don't need a
    backside. They function fully indepentant of other buses. If I assume you
    are talking about the HT link used to connect the K8 cpu's to the chipset,
    I'd just answer that it's in the same place as back side of the K7 CPU's
    FSB. You're really digging a hole for yourself here.

    >> IOW's using the term FSB
    >> specifically refers to the connection between the CPU and chipset,

    >
    > No, it doesn't. I specifically refers to the fact that the caches are on
    > the other side (back side) of the P6 memory bus. That architecture was
    > around for a while, so it stuck. There was no "FSB" in the P5
    > architecture. It's an invention of the P6 and should stay there, since
    > it no longer describes any function.
    >

    Why are you stuck on the Pentium Pro. FSB has been used for years to
    indicate the connection between the CPU and the chipset.
    >
    >> while
    >> using the term HT link could be any of many different type of
    >> connections an HT link is used for since it's used in many more
    >> applications than just a FSB. Some refer to the bus as a system bus,

    >
    > "System bus" works for me. I/O bus makes more sense.
    >

    Let's see, system buses. PCI, PCI-E, ISA, AGP, and others are all system
    buses. So how are you going to distinquish which one you are talking about
    if you just use system bus? Damn, I wonder if FSB would do that?:)
    I/O bus. Ditto, and you can throw HTlink into the mix too since it is also
    an I/O bus.

    --
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    Wes Newell, Sep 7, 2005
    #11
  12. On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell <>
    wrote:

    >On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:
    >
    >> On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:
    >>
    >>> FSB by definition connects the CPU to the chipset.

    >>
    >> Nope. As George stated, it was in opposition the "back-side <cache> bus"
    >> of the P6. The P5 had no "FSB".
    >>

    >Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let's
    >see just how many people you can convince of that.:)


    No, the K7s had (the equivalent of) a FSB though I'm not sure AMD ever
    called it that IIRC.

    >While the term may have originated the way you say, it was then later used
    >to indicate the connection between the CPU and the chipset. Now, that same
    >connection is the HT link of the K8. So it only makes sense to use the
    >same terminology for the very specific connection even though memory data
    >now has own single use bus for the memory. The FSB still carries all other
    >IO operations to/from the system. Once they move all this into the CPU,
    >there will no longer be a FSB. Until then, a duck by any other name is
    >still a duck.


    NO - the HT is more akin to the Intel Hub interface or the VIA-Link
    interconnect between memory controller/AGP chip and the I/O chip; it was
    AMD's attempt to establish a standard for that type of traffic... since
    Intel had locked theirs up with licensing fees. Much of the old PC North
    Bridge arbitration logic is now in the K8 CPU - it has to be to route to
    the various memory address spaces and for DMA transfers.

    >>> So given the choice of calling
    >>> the bus a FSB, or the HT link, FSB fits the bill while HT link only
    >>> describes the type of bus, not the bus itself.

    >>
    >> FSB doesn't describe it's function at all. What's the "back side" of
    >> the HT link?
    >>

    >What HT link? Ht links are used everywhere. AFAIK, they don't need a
    >backside. They function fully indepentant of other buses. If I assume you
    >are talking about the HT link used to connect the K8 cpu's to the chipset,
    >I'd just answer that it's in the same place as back side of the K7 CPU's
    >FSB. You're really digging a hole for yourself here.


    The equivalent of FSB on a K8 CPU is inside the CPU die - anything that
    gets out to HT is already defined as I/O traffic. In no way is it a FSB.

    --
    Rgds, George Macdonald
     
    George Macdonald, Sep 7, 2005
    #12
  13. "Wes Newell" <> wrote in message
    news:p...
    > On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:
    >
    > > On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:
    > >
    > >> FSB by definition connects the CPU to the chipset.

    > >
    > > Nope. As George stated, it was in opposition the "back-side

    <cache> bus"
    > > of the P6. The P5 had no "FSB".
    > >

    > Under your definition of FSB, then no AMD CPU's have ever had a FSB.

    Let's
    > see just how many people you can convince of that.:)


    Wes, are you saying no AMD chip ever had an L2 cache hung off the back
    of the CPU? Wow, is _my_ memory ever going south! ;-)
     
    Felger Carbon, Sep 7, 2005
    #13
  14. YKhan

    Wes Newell Guest

    On Wed, 07 Sep 2005 16:48:31 +0000, Felger Carbon wrote:

    > "Wes Newell" <> wrote in message
    > news:p...
    >> On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:
    >>
    >> > On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:
    >> >
    >> >> FSB by definition connects the CPU to the chipset.
    >> >
    >> > Nope. As George stated, it was in opposition the "back-side

    > <cache> bus"
    >> > of the P6. The P5 had no "FSB".
    >> >

    >> Under your definition of FSB, then no AMD CPU's have ever had a FSB.

    > Let's
    >> see just how many people you can convince of that.:)

    >
    > Wes, are you saying no AMD chip ever had an L2 cache hung off the back
    > of the CPU? Wow, is _my_ memory ever going south! ;-)


    Well, that's was what I said, but I wasn't thinking back past the K7 and
    K8's, and I actually never paid much attention to what they called the
    bus to the earlier cpu's that had cache on the MB. Was that an L2 cache? I
    thought it was L1. Too long ago to remember and I'm too lazy to look it up.:)
    And I just remembered that the Slot A k7's had it's L2 cache on the cpu
    board too, and not in the cpu die, but I don't recall AMD or anyone else
    using back side bus for it.

    --
    KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
    Need good help? Provide all system info with question.
    My server http://wesnewell.no-ip.com/cpu.php
    Verizon server http://mysite.verizon.net/res0exft/cpu.htm
     
    Wes Newell, Sep 7, 2005
    #14
  15. YKhan

    keith Guest

    On Wed, 07 Sep 2005 18:57:23 +0000, Wes Newell wrote:

    > On Wed, 07 Sep 2005 16:48:31 +0000, Felger Carbon wrote:
    >
    >> "Wes Newell" <> wrote in message
    >> news:p...
    >>> On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:
    >>>
    >>> > On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:
    >>> >
    >>> >> FSB by definition connects the CPU to the chipset.
    >>> >
    >>> > Nope. As George stated, it was in opposition the "back-side

    >> <cache> bus"
    >>> > of the P6. The P5 had no "FSB".
    >>> >
    >>> Under your definition of FSB, then no AMD CPU's have ever had a FSB.

    >> Let's
    >>> see just how many people you can convince of that.:)

    >>
    >> Wes, are you saying no AMD chip ever had an L2 cache hung off the back
    >> of the CPU? Wow, is _my_ memory ever going south! ;-)

    >
    > Well, that's was what I said, but I wasn't thinking back past the K7 and
    > K8's, and I actually never paid much attention to what they called the
    > bus to the earlier cpu's that had cache on the MB.


    K7s had the L2 on the "back side". It wasn't hooked into the external
    bus, as was socket-7 (and before).

    > Was that an L2 cache? I thought it was L1.


    Modern processors have *long* had seperate I and D L1s, burried in the
    instruction-fetch and load-store elements. The K7s L2 is certainly hung
    off the "back-side", meaning not connected to the system bus. The K8
    further seperates the I/O and memory busses, so there is no longer
    soethign even resembling a "front-side bus". There is (are) memory
    bus(ses) and HT link(s). Alghough, the HT link isn't just an I/O bus. It
    also crries coherency information (but I/O must be cache coherent too).

    > Too long ago to remember and
    > I'm too lazy to look it up.:) And I just remembered that the Slot A
    > k7's had it's L2 cache on the cpu board too, and not in the cpu die, but
    > I don't recall AMD or anyone else using back side bus for it.


    I'm from Missouri (close, but not really). I never remember a slot-A K7
    with on-board L2. Even the K6-III has an on-chip L2, but allows an
    on-board L3 (mine has a 2MB L3).

    --
    Keith
     
    keith, Sep 7, 2005
    #15
  16. YKhan

    Ed Guest

    On Wed, 07 Sep 2005 16:42:58 -0400, keith <> wrote:


    >
    >I'm from Missouri (close, but not really). I never remember a slot-A K7
    >with on-board L2. Even the K6-III has an on-chip L2, but allows an
    >on-board L3 (mine has a 2MB L3).


    Slot-A didn't have on-die L2 cache.
    K7-500 512K L2 (has a 650Mhz core)
    http://img9.imageshack.us/img9/6074/k7500650core0ch.jpg
     
    Ed, Sep 7, 2005
    #16
  17. YKhan

    keith Guest

    On Wed, 07 Sep 2005 16:53:57 -0500, Ed wrote:

    > On Wed, 07 Sep 2005 16:42:58 -0400, keith <> wrote:
    >
    >
    >>
    >>I'm from Missouri (close, but not really). I never remember a slot-A K7
    >>with on-board L2. Even the K6-III has an on-chip L2, but allows an
    >>on-board L3 (mine has a 2MB L3).

    >
    > Slot-A didn't have on-die L2 cache.


    I didn't say it did. Note that the Slot-1 PII didn't have an integrated
    cache either, but the cache was still on the "back side" of the chip. The
    Slot-A K7 was no different.

    > K7-500 512K L2 (has a 650Mhz core)
    > http://img9.imageshack.us/img9/6074/k7500650core0ch.jpg


    Sheesh, learn *SOMETHING*! Do start with reading comprehension.

    --
    Keith
     
    keith, Sep 8, 2005
    #17
  18. YKhan

    Tony Hill Guest

    On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell
    <> wrote:

    >On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:
    >
    >> On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:
    >>
    >>> FSB by definition connects the CPU to the chipset.

    >>
    >> Nope. As George stated, it was in opposition the "back-side <cache> bus"
    >> of the P6. The P5 had no "FSB".
    >>

    >Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let's
    >see just how many people you can convince of that.:)


    Not true at all. The original AMD Athlon had both a front-side bus,
    connecting the CPU to the chipset, I/O and memory, and a backside bus
    that connected the CPU to the cache chips on the Slot-A cartridge.
    This was actually the last x86 CPU that I'm aware of which did have a
    frontside bus (Intel had already gone to integrated cache by this
    time).

    Of course, the EV6 bus used to connect Athlon CPUs to their chipsets
    is only kinda-sorta a bus in itself. Really it's more of a
    point-to-point link, though it's in that fuzzy area that blurs the
    lines between the two a bit (where the GTL+ bus used in the P6 is
    definitely a bus and Hypertransport is definitely not a bus, EV6 falls
    somewhere in between).

    >While the term may have originated the way you say, it was then later used
    >to indicate the connection between the CPU and the chipset.


    Yes, a lot of people incorrectly refer to the a connection between the
    CPU and the chipset as a "Front Side Bus". Just because lots of
    people make a mistake that doesn't mean that they are right.

    People also still call the memory controller the "northbridge" and the
    I/O chip a "southbridge", which also makes no sense given that they
    are no longer being connected via PCI and they usually aren't bridges
    at all. Again, just because people incorrectly use a term doesn't
    make it correct.

    > Now, that same
    >connection is the HT link of the K8. So it only makes sense to use the
    >same terminology for the very specific connection even though memory data
    >now has own single use bus for the memory.


    It doesn't make any sense with the AthlonXP or the P4 and it makes
    MUCH less sense with the Athlon64/Opteron. Just because it's a common
    mistake doesn't make it any less of a mistake.

    > The FSB still carries all other
    >IO operations to/from the system. Once they move all this into the CPU,
    >there will no longer be a FSB. Until then, a duck by any other name is
    >still a duck.


    Yes, but that still doesn't make a goose a duck, even if lots of
    people mix the two of them up.

    >> FSB doesn't describe it's function at all. What's the "back side" of
    >> the HT link?
    >>

    >What HT link? Ht links are used everywhere. AFAIK, they don't need a
    >backside.


    The point is that you can't have a "front side bus" unless you have a
    corresponding "back side bus". Hypertransport does not have such a
    corresponding back side so therefore it's not the "front side" of
    anything.

    Given that it's not the 'front side' of anything and, as others have
    mentioned, it's not a 'bus' at all then it DEFINITELY is not a "Front
    Side Bus".

    > They function fully indepentant of other buses. If I assume you
    >are talking about the HT link used to connect the K8 cpu's to the chipset,
    >I'd just answer that it's in the same place as back side of the K7 CPU's
    >FSB. You're really digging a hole for yourself here.


    The original Athlon had a backside bus with to the cache chips on the
    cartridge. This was later removed with the "Thunderbird" chips with
    integrated cache. As such, from the "Thunderbird" on forward
    (including all AthlonXP chips) there was no FSB on the AthlonXP. Same
    goes for the PIII from the "Coppermine" onwards as well as ALL P4
    chips. None of those have FSBs, despite the fact that many people
    incorrectly use the term to describe the system bus of said chips.

    >>> IOW's using the term FSB
    >>> specifically refers to the connection between the CPU and chipset,

    >>
    >> No, it doesn't. I specifically refers to the fact that the caches are on
    >> the other side (back side) of the P6 memory bus. That architecture was
    >> around for a while, so it stuck. There was no "FSB" in the P5
    >> architecture. It's an invention of the P6 and should stay there, since
    >> it no longer describes any function.
    >>

    >Why are you stuck on the Pentium Pro. FSB has been used for years to
    >indicate the connection between the CPU and the chipset.


    The term "Front Side Bus" was never used with the Pentium chips
    because there was only one bus. FSB came into computer use with the
    PentiumPro where Intel introduced a chip with a Frontside Bus
    (connecting to main memory and I/O) and a Backside bus (connecting to
    cache). The terminology continued through the PII and early PIII
    chips, as well as early Athlon chips, as they had two buses, one for
    memory and I/O and the other for cache. For chips with only a single
    bus the term "FSB" makes no sense. Never has and never will, no
    matter how many people make such a mistake.

    With the Athlon64 and Opteron it's just more obviously incorrect than
    it is with the AthlonXP and P4 chips.

    >>> while
    >>> using the term HT link could be any of many different type of
    >>> connections an HT link is used for since it's used in many more
    >>> applications than just a FSB. Some refer to the bus as a system bus,

    >>
    >> "System bus" works for me. I/O bus makes more sense.
    >>

    >Let's see, system buses. PCI, PCI-E, ISA, AGP, and others are all system
    >buses. So how are you going to distinquish which one you are talking about
    >if you just use system bus? Damn, I wonder if FSB would do that?:)
    >I/O bus. Ditto, and you can throw HTlink into the mix too since it is also
    >an I/O bus.


    Hypertransport is NOT an 'bus' in any way, shape or form. HT is a
    point-to-point link. PCI-E and AGP are also definitely not buses,
    though I expect many people to incorrectly call them such. PCI and
    ISA are buses

    -------------
    Tony Hill
    hilla <underscore> 20 <at> yahoo <dot> ca
     
    Tony Hill, Sep 9, 2005
    #18
  19. YKhan

    Tony Hill Guest

    On Wed, 07 Sep 2005 16:42:58 -0400, keith <> wrote:
    >> Too long ago to remember and
    >> I'm too lazy to look it up.:) And I just remembered that the Slot A
    >> k7's had it's L2 cache on the cpu board too, and not in the cpu die, but
    >> I don't recall AMD or anyone else using back side bus for it.

    >
    >I'm from Missouri (close, but not really). I never remember a slot-A K7
    >with on-board L2.


    There were a *few* Slot-A K7 chips that had integrated L2, but they
    were only released for compatibility purposes (much like what Intel
    did with some of their later Slot-1 PIII chips, though AMD released
    far fewer of such chips). You might even be able to find someone
    still selling such a beast if you look hard enough, just do a search
    for "Thunderbird Slot-A".

    -------------
    Tony Hill
    hilla <underscore> 20 <at> yahoo <dot> ca
     
    Tony Hill, Sep 9, 2005
    #19
  20. YKhan

    Wes Newell Guest

    On Thu, 08 Sep 2005 21:41:35 -0400, Tony Hill wrote:

    > On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell
    > <> wrote:
    >
    >>On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:
    >>
    >>> On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:
    >>>
    >>>> FSB by definition connects the CPU to the chipset.
    >>>
    >>> Nope. As George stated, it was in opposition the "back-side <cache> bus"
    >>> of the P6. The P5 had no "FSB".
    >>>

    >>Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let's
    >>see just how many people you can convince of that.:)

    >
    > Not true at all. The original AMD Athlon had both a front-side bus,
    > connecting the CPU to the chipset, I/O and memory, and a backside bus
    > that connected the CPU to the cache chips on the Slot-A cartridge.
    > This was actually the last x86 CPU that I'm aware of which did have a
    > frontside bus (Intel had already gone to integrated cache by this
    > time).


    You're partially right anyway.:)
    >
    > Of course, the EV6 bus used to connect Athlon CPUs to their chipsets
    > is only kinda-sorta a bus in itself. Really it's more of a
    > point-to-point link, though it's in that fuzzy area that blurs the
    > lines between the two a bit (where the GTL+ bus used in the P6 is
    > definitely a bus and Hypertransport is definitely not a bus, EV6 falls
    > somewhere in between).
    >

    You're out to lunch here for the most part.

    >>While the term may have originated the way you say, it was then later
    >>used to indicate the connection between the CPU and the chipset.

    >
    > Yes, a lot of people incorrectly refer to the a connection between the
    > CPU and the chipset as a "Front Side Bus". Just because lots of people
    > make a mistake that doesn't mean that they are right.
    >

    Wrong. FSB is defined as the bus connection between the CPU and chipset.
    AMD calls the bus a FSB and I'm pretty sure Intel did too on the P4. If
    you break down the term, it's pretty simple. Front side, meaning not the
    back side, and bus. A bus is a collection of 1 or more electrical
    connections between 2 or more points. The type of bus (standard, EV6, HT
    link, or any other type) is of no concern.

    > People also still call the memory controller the "northbridge" and the
    > I/O chip a "southbridge", which also makes no sense given that they are
    > no longer being connected via PCI and they usually aren't bridges at
    > all. Again, just because people incorrectly use a term doesn't make it
    > correct.
    >

    What? The northbridge has much more in it than just a memory controller.
    And the K8 northbridge doesn't even have a memory controller in it.

    >> Now, that same
    >>connection is the HT link of the K8. So it only makes sense to use the
    >>same terminology for the very specific connection even though memory
    >>data now has own single use bus for the memory.

    >
    > It doesn't make any sense with the AthlonXP or the P4 and it makes MUCH
    > less sense with the Athlon64/Opteron. Just because it's a common
    > mistake doesn't make it any less of a mistake.
    >

    Well, AMD and Intel disagree, as do I. ANd it's used for one purpose IMO,
    to distinquish which fricking bus you are talking about.

    >> The FSB still carries all other
    >>IO operations to/from the system. Once they move all this into the CPU,
    >>there will no longer be a FSB. Until then, a duck by any other name is
    >>still a duck.

    >
    > Yes, but that still doesn't make a goose a duck, even if lots of people
    > mix the two of them up.
    >

    Just out of curiosty, I'd like you to tell me what the name of the bus
    is between the CPU and the chipset. And I don't mean what type of bus.
    It's already known to be an HT link. So what's the name you want to give
    it so that when someone refers to it by that name they will know exactly
    which bus you are talking about and where it connects. And it has to be
    specific. Sytem bus doesn't cut, there's many system buses. CPU bus
    doesn't cut it as there are many cpu busses if you count the internal
    busses. I say FSB. I'm waiting for a better one from you.

    >
    > The point is that you can't have a "front side bus" unless you have a
    > corresponding "back side bus". Hypertransport does not have such a
    > corresponding back side so therefore it's not the "front side" of
    > anything.
    >

    I'll give you two options. Take your pick. (1) The internal bus to the L2
    cache is the back side bus. It just internal now. (2) Why must there be a
    BSB at all? FSB is more of a designation for a certain bus rather than
    actually describing it's location. It connects between the CPU and
    chipset, just as it did on the Athlon (non 64) cpu's. And no one had any
    complaints of calling it a FSB then. That's what AMD called it.

    >> They function fully indepentant of other buses. If I assume you
    >>are talking about the HT link used to connect the K8 cpu's to the
    >>chipset, I'd just answer that it's in the same place as back side of the
    >>K7 CPU's FSB. You're really digging a hole for yourself here.

    >
    > The original Athlon had a backside bus with to the cache chips on the
    > cartridge. This was later removed with the "Thunderbird" chips with
    > integrated cache. As such, from the "Thunderbird" on forward (including
    > all AthlonXP chips) there was no FSB on the AthlonXP.


    They didn't remove the L2 cache. It was just moved inside the die. You
    think that memory just magically connects to the rest of the CPU without
    a bus. I sure as hell wish I'd known I could do that when I was designing
    memory controllers.:)

    > Same goes for the
    > PIII from the "Coppermine" onwards as well as ALL P4 chips. None of
    > those have FSBs, despite the fact that many people incorrectly use the
    > term to describe the system bus of said chips.
    >

    I'm not an Intel user, but I assume you are as wrong about this as you are
    about the AMD's not having a FSB.

    >>Why are you stuck on the Pentium Pro. FSB has been used for years to
    >>indicate the connection between the CPU and the chipset.

    >
    > The term "Front Side Bus" was never used with the Pentium chips because
    > there was only one bus. FSB came into computer use with the PentiumPro
    > where Intel introduced a chip with a Frontside Bus (connecting to main
    > memory and I/O) and a Backside bus (connecting to cache).


    How many times must you guys write this? No one argues that point.

    > The terminology continued through the PII and early PIII chips, as well
    > as early Athlon chips, as they had two buses, one for memory and I/O
    > and the other for cache. For chips with only a single bus the term "FSB"
    > makes no sense. Never has and never will, no matter how many people
    > make such a mistake.
    >

    It makes all the sense in the world defined as the connection between the
    CPU and chipset. If not, tell me what does. All you people have said it's
    not right, yet none of you have come up with a definitive name for the
    bus. I wonder if that's why it's stuck around so long, since I've seen it
    defined as just that, the bus between the CPU and chipset.

    > With the Athlon64 and Opteron it's just more obviously incorrect than it
    > is with the AthlonXP and P4 chips.
    >

    Tell AMD and Intel, they need some humor too.

    > Hypertransport is NOT an 'bus' in any way, shape or form. HT is a
    > point-to-point link. PCI-E and AGP are also definitely not buses,
    > though I expect many people to incorrectly call them such. PCI and ISA
    > are buses


    I don't know what you think a bus is. perhaps you should give your
    definition of a bus, and not a school bus. Every definition of bus I've
    seen says it an electrical pathway. So unless the HT link works without
    electricty, it's a bus. As are all the others you claim aren't.

    And now the killer punch. From;

    http://www.hypertransport.org/consortium/cons_faqs.cfm

    9. How does HyperTransport technology compare to other bus technologies?

    As compared to older multidrop, shared buses such as PCI, PCI-X or SysAD,
    HyperTransport provides a far simplier electrical interface, but with much
    greater bandwidth. Instead of a wide, address/data/control multidrop,
    shared bus such as implemented by PCI, PCI-X or SysAD technologies,
    HyperTransport deploys narrow, but very fast unidirectional links to carry
    both data and command information encoded into packets. Unidirectional
    links provide significantly better signal integrity at high speeds and
    enable much faster data transfers with low-power 1.2V LVDS signals. In
    addition, link widths can be asymmetrical, meaning that 2 bit wide links
    can easily connect to 8 bit wide links and 8 bit wide links can connect to
    16 or 32 bit wide links and so on. Thus, the HyperTransport Technology
    eliminates the problems associated with high speed parallel buses with
    their many noisy bus signals (multiplexed data/address, and clock and
    control signals) while providing scalable bandwidth wherever it is needed
    in the system. As compared to newer serial I/O technologies such as
    RapidIO and PCI Express, HyperTransport shares some raw bandwidth
    characteristics, but is significantly different in some key
    characteristics.
    *****Read this pargraph carefully********
    HyperTransport was designed to support both CPU-to-CPU
    communications as well as CPU-to-I/O transfers, thus, it features very low
    latency. Consequently, it has been incorporated into multiple x86 and MIPS
    architecture processors as an integrated front-side bus.
    *And don't miss this................................. ^^^^^^^^^ *

    Serial technologies such as PCI Express and RapidIO require
    serial-deserializer interfaces and have the burden of extensive overhead
    in encoding parallel data into serial data, embedding clock information,
    re-acquiring and decoding the data stream. The parallel technology of
    HyperTransport needs no serdes and clock encoding overhead making it far
    more efficient in data transfers.

    I rest my case.;-)

    --
    KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
    Need good help? Provide all system info with question.
    My server http://wesnewell.no-ip.com/cpu.php
    Verizon server http://mysite.verizon.net/res0exft/cpu.htm
     
    Wes Newell, Sep 9, 2005
    #20
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