AMD also made an announcement today about a new version of SSE, called
SSE5. It looks like it's forking off SSE from Intel, because Intel is
getting ready to introduce SSE4 in its upcoming Penryn processors. AMD
plans to introduce SSE5 in its own next-generation Bulldozer line of
processors which will integrate a GPU into the chip package. The problem
is that there doesn't seem to be too much overlap between Intel's SSE4
and AMD's SSE5. AMD doesn't seem like it's going to integrate Intel's
new SSE4 instructions, and who knows what Intel will do with the new AMD
SSE5 instructions (well, actually we really do know what Intel will do).
:-)
Anyways one of the highlights of SSE5 is that it introduces 3-operand
instructions into x86. This makes it more comparable to the old AltiVec
instruction set from the old Apple Macintoshes using PowerPCs. It also
introduces a 16-bit "half-precision" floating point format, probably to
accomodate GPUs.
The 3-operand instructions will be of the format:
INSTR dest, src1, src2, src3
But the "dest" register will be the same as either the "src1" or "src3"
registers, it won't be a 4th register.
http://www.arstechnica.com/news.ars/...ns-to-x86.html
Yousuf Khan
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