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Re: Gaming AMD vs Intel

 
 
Del Cecchi
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      9th Sep 2005
Wes Newell wrote:
*
snip
>
> Serial technologies such as PCI Express and RapidIO require
> serial-deserializer interfaces and have the burden of extensive overhead
> in encoding parallel data into serial data, embedding clock information,
> re-acquiring and decoding the data stream. The parallel technology of
> HyperTransport needs no serdes and clock encoding overhead making it far
> more efficient in data transfers.
>
> I rest my case.;-)
>


The last paragraph you quote, shown above, is Clintonian at best, with
respect to comparing the physical aspects of HT and PCI-E.

--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.”
 
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keith
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      9th Sep 2005
On Thu, 08 Sep 2005 21:41:36 -0400, Tony Hill wrote:

> On Wed, 07 Sep 2005 16:42:58 -0400, keith <(E-Mail Removed)> wrote:
>>> Too long ago to remember and
>>> I'm too lazy to look it up.:-) And I just remembered that the Slot A
>>> k7's had it's L2 cache on the cpu board too, and not in the cpu die, but
>>> I don't recall AMD or anyone else using back side bus for it.

>>
>>I'm from Missouri (close, but not really). I never remember a slot-A K7
>>with on-board L2.

>
> There were a *few* Slot-A K7 chips that had integrated L2, but they
> were only released for compatibility purposes (much like what Intel
> did with some of their later Slot-1 PIII chips, though AMD released
> far fewer of such chips). You might even be able to find someone
> still selling such a beast if you look hard enough, just do a search
> for "Thunderbird Slot-A".


I meant the cache on the board (system bus), as opposed to "integrated"
or on the cartridge (on the "back-side").

--
Keith
 
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keith
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      9th Sep 2005
On Thu, 08 Sep 2005 21:41:35 -0400, Tony Hill wrote:

> On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell
> <(E-Mail Removed)> wrote:
>
>>On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:
>>
>>> On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:
>>>
>>>> FSB by definition connects the CPU to the chipset.
>>>
>>> Nope. As George stated, it was in opposition the "back-side <cache> bus"
>>> of the P6. The P5 had no "FSB".
>>>

>>Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let's
>>see just how many people you can convince of that.:-)

>
> Not true at all. The original AMD Athlon had both a front-side bus,
> connecting the CPU to the chipset, I/O and memory, and a backside bus
> that connected the CPU to the cache chips on the Slot-A cartridge.
> This was actually the last x86 CPU that I'm aware of which did have a
> frontside bus (Intel had already gone to integrated cache by this
> time).


Just because the cache is integrated doesn't mean the cache isn't on the
"back side" of the processor. The "back-side" concept was really a
separation of the cache from the memory busses.

> Of course, the EV6 bus used to connect Athlon CPUs to their chipsets is
> only kinda-sorta a bus in itself. Really it's more of a point-to-point
> link, though it's in that fuzzy area that blurs the lines between the
> two a bit (where the GTL+ bus used in the P6 is definitely a bus and
> Hypertransport is definitely not a bus, EV6 falls somewhere in between).


Works for me.

>>While the term may have originated the way you say, it was then later
>>used to indicate the connection between the CPU and the chipset.

>
> Yes, a lot of people incorrectly refer to the a connection between the
> CPU and the chipset as a "Front Side Bus". Just because lots of people
> make a mistake that doesn't mean that they are right.


Yep! It ignores the reason it was called the "front-side bus" to begin
with.

> People also still call the memory controller the "northbridge" and the
> I/O chip a "southbridge", which also makes no sense given that they are
> no longer being connected via PCI and they usually aren't bridges at
> all. Again, just because people incorrectly use a term doesn't make it
> correct.


As long as there is an off-chip memory controller and high-speed
peripherals on the "bridge", it's proper to call it a "north-bridge". If
there is a low-spped bridge hanging off that, "south-bridge" is a useful
concept.

>> Now, that same
>>connection is the HT link of the K8. So it only makes sense to use the
>>same terminology for the very specific connection even though memory
>>data now has own single use bus for the memory.

>
> It doesn't make any sense with the AthlonXP or the P4 and it makes MUCH
> less sense with the Athlon64/Opteron. Just because it's a common
> mistake doesn't make it any less of a mistake.


Why doesn't "front-side bus" work with the P4 or K7? The cache is still
on the "back side" of the processor, even though it's on the chip.

<snip>

>> They function fully indepentant of other buses. If I assume you
>>are talking about the HT link used to connect the K8 cpu's to the
>>chipset, I'd just answer that it's in the same place as back side of the
>>K7 CPU's FSB. You're really digging a hole for yourself here.

>
> The original Athlon had a backside bus with to the cache chips on the
> cartridge. This was later removed with the "Thunderbird" chips with
> integrated cache. As such, from the "Thunderbird" on forward (including
> all AthlonXP chips) there was no FSB on the AthlonXP. Same goes for the
> PIII from the "Coppermine" onwards as well as ALL P4 chips. None of
> those have FSBs, despite the fact that many people incorrectly use the
> term to describe the system bus of said chips.


No, the back side bus wasn't removed. It was integrated onto the chip.
The architecture is the same, if the parts moved around.

>>>> IOW's using the term FSB
>>>> specifically refers to the connection between the CPU and chipset,
>>>
>>> No, it doesn't. I specifically refers to the fact that the caches are
>>> on the other side (back side) of the P6 memory bus. That architecture
>>> was around for a while, so it stuck. There was no "FSB" in the P5
>>> architecture. It's an invention of the P6 and should stay there,
>>> since it no longer describes any function.
>>>

>>Why are you stuck on the Pentium Pro. FSB has been used for years to
>>indicate the connection between the CPU and the chipset.

>
> The term "Front Side Bus" was never used with the Pentium chips because
> there was only one bus. FSB came into computer use with the PentiumPro
> where Intel introduced a chip with a Frontside Bus (connecting to main
> memory and I/O) and a Backside bus (connecting to cache). The
> terminology continued through the PII and early PIII chips, as well as
> early Athlon chips, as they had two buses, one for memory and I/O and
> the other for cache. For chips with only a single bus the term "FSB"
> makes no sense. Never has and never will, no matter how many people
> make such a mistake.


I dissagree. The back-side bus was integrated onto the chip. Again, the
memory architecture was the same.

> With the Athlon64 and Opteron it's just more obviously incorrect than it
> is with the AthlonXP and P4 chips.


It *is* incorrect, not so with the P4 or K7.

>>>> while
>>>> using the term HT link could be any of many different type of
>>>> connections an HT link is used for since it's used in many more
>>>> applications than just a FSB. Some refer to the bus as a system bus,
>>>
>>> "System bus" works for me. I/O bus makes more sense.
>>>

>>Let's see, system buses. PCI, PCI-E, ISA, AGP, and others are all system
>>buses. So how are you going to distinquish which one you are talking
>>about if you just use system bus? Damn, I wonder if FSB would do
>>that?:-) I/O bus. Ditto, and you can throw HTlink into the mix too since
>>it is also an I/O bus.


> Hypertransport is NOT an 'bus' in any way, shape or form. HT is a
> point-to-point link. PCI-E and AGP are also definitely not buses,
> though I expect many people to incorrectly call them such. PCI and ISA
> are buses


True enough. Apparently some people call ducks geese too. ;-)

--
Keith

 
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Wes Newell
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      9th Sep 2005
On Fri, 09 Sep 2005 10:01:26 -0500, Del Cecchi wrote:

> Wes Newell wrote:
> *
> snip
>>
>> Serial technologies such as PCI Express and RapidIO require
>> serial-deserializer interfaces and have the burden of extensive overhead
>> in encoding parallel data into serial data, embedding clock information,
>> re-acquiring and decoding the data stream. The parallel technology of
>> HyperTransport needs no serdes and clock encoding overhead making it far
>> more efficient in data transfers.
>>
>> I rest my case.;-)
>>

>
> The last paragraph you quote, shown above, is Clintonian at best, with
> respect to comparing the physical aspects of HT and PCI-E.


You snipped the portion I had highlighted. I didn't even read this part.
Nor do I have any comments on it. If you have a problem with it. i suggest
you contact the people that wrote it. If Clintonian refers to refers to
our lying crooked x pres, those are are fighting words. I never voted for
the lowlife.

--
KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
Need good help? Provide all system info with question.
My server http://wesnewell.no-ip.com/cpu.php
Verizon server http://mysite.verizon.net/res0exft/cpu.htm

 
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Del Cecchi
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      9th Sep 2005
Wes Newell wrote:
> On Fri, 09 Sep 2005 10:01:26 -0500, Del Cecchi wrote:
>
>
>>Wes Newell wrote:
>>*
>>snip
>>
>>>Serial technologies such as PCI Express and RapidIO require
>>>serial-deserializer interfaces and have the burden of extensive overhead
>>>in encoding parallel data into serial data, embedding clock information,
>>>re-acquiring and decoding the data stream. The parallel technology of
>>>HyperTransport needs no serdes and clock encoding overhead making it far
>>>more efficient in data transfers.
>>>
>>>I rest my case.;-)
>>>

>>
>>The last paragraph you quote, shown above, is Clintonian at best, with
>>respect to comparing the physical aspects of HT and PCI-E.

>
>
> You snipped the portion I had highlighted. I didn't even read this part.
> Nor do I have any comments on it. If you have a problem with it. i suggest
> you contact the people that wrote it. If Clintonian refers to refers to
> our lying crooked x pres, those are are fighting words. I never voted for
> the lowlife.
>

You pasted and posted, from the HT Marketroids. They were doing fine
until this paragraph which is Clintonian in its mixture of half truth
and fibs. I never thought you personally were responsible.

HT sacrificed all for low latency and low cost in the first couple
versions. "Network Extensions" started to fix it, and I have hopes for
HT3 when it comes out.

--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.”
 
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George Macdonald
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      9th Sep 2005
On Fri, 09 Sep 2005 04:52:36 GMT, Wes Newell <(E-Mail Removed)>
wrote:

>On Thu, 08 Sep 2005 21:41:35 -0400, Tony Hill wrote:
>
>> On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell
>> <(E-Mail Removed)> wrote:
>>


>>>> Nope. As George stated, it was in opposition the "back-side <cache> bus"
>>>> of the P6. The P5 had no "FSB".
>>>>
>>>Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let's
>>>see just how many people you can convince of that.:-)

>> Of course, the EV6 bus used to connect Athlon CPUs to their chipsets
>> is only kinda-sorta a bus in itself. Really it's more of a
>> point-to-point link, though it's in that fuzzy area that blurs the
>> lines between the two a bit (where the GTL+ bus used in the P6 is
>> definitely a bus and Hypertransport is definitely not a bus, EV6 falls
>> somewhere in between).
>>

>You're out to lunch here for the most part.


If you go look up some tech docs & data sheets you'll find that he's spot
on... as usual. EV6 is not a bus by the usual criteria.

>>>While the term may have originated the way you say, it was then later
>>>used to indicate the connection between the CPU and the chipset.

>>
>> Yes, a lot of people incorrectly refer to the a connection between the
>> CPU and the chipset as a "Front Side Bus". Just because lots of people
>> make a mistake that doesn't mean that they are right.
>>

>Wrong. FSB is defined as the bus connection between the CPU and chipset.
>AMD calls the bus a FSB and I'm pretty sure Intel did too on the P4.


You'll have to cite a technical reference for AMD calling the HT link to
the I/O chip(s) a FSB - brewing up your own folksy lexicon for computer
sub-system nomenclature will not do it.

> If
>you break down the term, it's pretty simple. Front side, meaning not the
>back side, and bus. A bus is a collection of 1 or more electrical
>connections between 2 or more points. The type of bus (standard, EV6, HT
>link, or any other type) is of no concern.


If we allow a bit of slack and call the on-die L2 cache connection a BSB,
we can call the K7s', P4s', P-Ms' connection to the chipset a FSB - after
all it carries the same traffic as a FSB. AMD has used this terminology
for its K7 architecture though some have argued with that. With the K8 the
HT link to to the I/O sub-system, however, there is no CPU<-> memory
traffic, which is the principal function of a FSB and is the derivation of
the name; the up/down HT link doesn't even serve the same functions as a
FSB.

>> People also still call the memory controller the "northbridge" and the
>> I/O chip a "southbridge", which also makes no sense given that they are
>> no longer being connected via PCI and they usually aren't bridges at
>> all. Again, just because people incorrectly use a term doesn't make it
>> correct.
>>

>What? The northbridge has much more in it than just a memory controller.
>And the K8 northbridge doesn't even have a memory controller in it.


<cough><splutter> You just fell in.

The K8 architecture does not have a north bridge... and in the case of
nForce3/4 has only the one chip for I/O and AGP/PCI-e Tunnel.

>>> Now, that same
>>>connection is the HT link of the K8. So it only makes sense to use the
>>>same terminology for the very specific connection even though memory
>>>data now has own single use bus for the memory.

>>
>> It doesn't make any sense with the AthlonXP or the P4 and it makes MUCH
>> less sense with the Athlon64/Opteron. Just because it's a common
>> mistake doesn't make it any less of a mistake.
>>

>Well, AMD and Intel disagree, as do I. ANd it's used for one purpose IMO,
>to distinquish which fricking bus you are talking about.


I won't argue about K7/P4/P-M but for K8.... references.

>>> The FSB still carries all other
>>>IO operations to/from the system. Once they move all this into the CPU,
>>>there will no longer be a FSB. Until then, a duck by any other name is
>>>still a duck.

>>
>> Yes, but that still doesn't make a goose a duck, even if lots of people
>> mix the two of them up.
>>

>Just out of curiosty, I'd like you to tell me what the name of the bus
>is between the CPU and the chipset. And I don't mean what type of bus.
>It's already known to be an HT link. So what's the name you want to give
>it so that when someone refers to it by that name they will know exactly
>which bus you are talking about and where it connects. And it has to be
>specific. Sytem bus doesn't cut, there's many system buses. CPU bus
>doesn't cut it as there are many cpu busses if you count the internal
>busses. I say FSB. I'm waiting for a better one from you.


AMD has used the term "I/O connection" when HT connects the CPU to an I/O
chipset; before Pentium Pro it was called system bus or IIRC main bus or
even main system bus.

>> The point is that you can't have a "front side bus" unless you have a
>> corresponding "back side bus". Hypertransport does not have such a
>> corresponding back side so therefore it's not the "front side" of
>> anything.
>>

>I'll give you two options. Take your pick. (1) The internal bus to the L2
>cache is the back side bus. It just internal now. (2) Why must there be a
>BSB at all? FSB is more of a designation for a certain bus rather than
>actually describing it's location. It connects between the CPU and
>chipset, just as it did on the Athlon (non 64) cpu's. And no one had any
>complaints of calling it a FSB then. That's what AMD called it.


Again, the most important task of a FSB has been CPU<->memory traffic - the
K8's HT doesn't do that... different topology... it's not an FSB.

>>>Why are you stuck on the Pentium Pro. FSB has been used for years to
>>>indicate the connection between the CPU and the chipset.

>>
>> The term "Front Side Bus" was never used with the Pentium chips because
>> there was only one bus. FSB came into computer use with the PentiumPro
>> where Intel introduced a chip with a Frontside Bus (connecting to main
>> memory and I/O) and a Backside bus (connecting to cache).

>
>How many times must you guys write this? No one argues that point.


But you just did - you asked why we were "stuck" on Pentium Pro... the
origin of the term FSB.

>> The terminology continued through the PII and early PIII chips, as well
>> as early Athlon chips, as they had two buses, one for memory and I/O
>> and the other for cache. For chips with only a single bus the term "FSB"
>> makes no sense. Never has and never will, no matter how many people
>> make such a mistake.
>>

>It makes all the sense in the world defined as the connection between the
>CPU and chipset. If not, tell me what does. All you people have said it's
>not right, yet none of you have come up with a definitive name for the
>bus. I wonder if that's why it's stuck around so long, since I've seen it
>defined as just that, the bus between the CPU and chipset.


No it makes no sense at all, since by definition, as the cohort of a BSB,
it carries CPU<->memory traffic. To belabor the point: the BSB carried
CPU<->L2 Cache traffic and on cache misses, the traffic is "diverted" to
FSB.

>> Hypertransport is NOT an 'bus' in any way, shape or form. HT is a
>> point-to-point link. PCI-E and AGP are also definitely not buses,
>> though I expect many people to incorrectly call them such. PCI and ISA
>> are buses

>
>I don't know what you think a bus is. perhaps you should give your
>definition of a bus, and not a school bus. Every definition of bus I've
>seen says it an electrical pathway. So unless the HT link works without
>electricty, it's a bus. As are all the others you claim aren't.


You are (apparently) confused by an electrician's bus and a computer
architect's bus. To some system experts/architects -- and there is at
least one of them arguing with you -- the term "bus" implies "multi-drop
bus", as is the case with Intel's GTL+ and AGTL+. It is also often used
more loosely, as is the case of K7. When it is used with an accompanying
qualifier, like PCI Bus, USB, FSB etc. it is generally a specific
designation for something which is well, even formally, defined
functionality. In K8, HT does not fulfill the same functionality as FSB.

>And now the killer punch. From;
>
>http://www.hypertransport.org/consortium/cons_faqs.cfm
>
>9. How does HyperTransport technology compare to other bus technologies?
>
>As compared to older multidrop, shared buses such as PCI, PCI-X or SysAD,
>HyperTransport provides a far simplier electrical interface, but with much
>greater bandwidth. Instead of a wide, address/data/control multidrop,
>shared bus such as implemented by PCI, PCI-X or SysAD technologies,
>HyperTransport deploys narrow, but very fast unidirectional links to carry
>both data and command information encoded into packets. Unidirectional
>links provide significantly better signal integrity at high speeds and
>enable much faster data transfers with low-power 1.2V LVDS signals. In
>addition, link widths can be asymmetrical, meaning that 2 bit wide links
>can easily connect to 8 bit wide links and 8 bit wide links can connect to
>16 or 32 bit wide links and so on. Thus, the HyperTransport Technology
>eliminates the problems associated with high speed parallel buses with
>their many noisy bus signals (multiplexed data/address, and clock and
>control signals) while providing scalable bandwidth wherever it is needed
>in the system. As compared to newer serial I/O technologies such as
>RapidIO and PCI Express, HyperTransport shares some raw bandwidth
>characteristics, but is significantly different in some key
>characteristics.
>*****Read this pargraph carefully********
> HyperTransport was designed to support both CPU-to-CPU
>communications as well as CPU-to-I/O transfers, thus, it features very low
>latency. Consequently, it has been incorporated into multiple x86 and MIPS
>architecture processors as an integrated front-side bus.
>*And don't miss this................................. ^^^^^^^^^ *
>
>Serial technologies such as PCI Express and RapidIO require
>serial-deserializer interfaces and have the burden of extensive overhead
>in encoding parallel data into serial data, embedding clock information,
>re-acquiring and decoding the data stream. The parallel technology of
>HyperTransport needs no serdes and clock encoding overhead making it far
>more efficient in data transfers.
>
>I rest my case.;-)


What can I say?... somebody blundered... it's only a FAQ and "*integrated*
front side bus" is the only place where it refers to HT as a "bus". If you
look at
http://www.amd.com/us-en/assets/cont...ure_FINAL2.pdf
on p8 you'll find "Replacing what has traditionally been the system
'front-side bus' with a HyperTransport technology-based I/O connection
dramatically extends processor to system communication bandwidth from
2.1GB/s up to 6.4GB/s". There are pictures for you of the old FSB
architecture and the new HT-based architecture. Then on p9:
"HyperTransport technology provides a high-speed, chip-to-chip
interconnect..."

--
Rgds, George Macdonald
 
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Wes Newell
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Posts: n/a
 
      10th Sep 2005
On Fri, 09 Sep 2005 18:23:25 -0400, George Macdonald wrote:

> On Fri, 09 Sep 2005 04:52:36 GMT, Wes Newell <(E-Mail Removed)>
> wrote:
>>You're out to lunch here for the most part.

>
> If you go look up some tech docs & data sheets you'll find that he's spot
> on... as usual. EV6 is not a bus by the usual criteria.
>

Suggest you read this. One of thousands that claim it's a bus.

http://www.free-definition.com/Front-side-bus.html

>>Wrong. FSB is defined as the bus connection between the CPU and chipset.
>>AMD calls the bus a FSB and I'm pretty sure Intel did too on the P4.

>
> You'll have to cite a technical reference for AMD calling the HT link to
> the I/O chip(s) a FSB - brewing up your own folksy lexicon for computer
> sub-system nomenclature will not do it.
>

I'm not wasting any more time citing crap for you. The proof is down
below, which you tend to ignore.

>> If
>>you break down the term, it's pretty simple. Front side, meaning not the
>>back side, and bus. A bus is a collection of 1 or more electrical
>>connections between 2 or more points. The type of bus (standard, EV6, HT
>>link, or any other type) is of no concern.

>
> If we allow a bit of slack and call the on-die L2 cache connection a
> BSB, we can call the K7s', P4s', P-Ms' connection to the chipset a FSB -
> after all it carries the same traffic as a FSB. AMD has used this
> terminology for its K7 architecture though some have argued with that.
> With the K8 the HT link to to the I/O sub-system, however, there is no
> CPU<-> memory traffic, which is the principal function of a FSB and is
> the derivation of the name; the up/down HT link doesn't even serve the
> same functions as a FSB.
>

The cpu to system memory function was just one of many functions the FSB
does. it still has cpu to memory functions and feeds data to/from the
memory on the video card, the cache memory on each hard drive, memory on
other cards, etc, etc, etc.

>>What? The northbridge has much more in it than just a memory controller.
>>And the K8 northbridge doesn't even have a memory controller in it.

>
> <cough><splutter> You just fell in.
>

I meant the chipset northbridge.

> The K8 architecture does not have a north bridge... and in the case of
> nForce3/4 has only the one chip for I/O and AGP/PCI-e Tunnel.
>
>>Well, AMD and Intel disagree, as do I. ANd it's used for one purpose
>>IMO, to distinquish which fricking bus you are talking about.

>
> I won't argue about K7/P4/P-M but for K8.... references.
>

You already seen them from the Hyprtansport Consortium. Who do you want
them from before you will believe it, God? Sorry, can't help you there.

>>Just out of curiosty, I'd like you to tell me what the name of the bus
>>is between the CPU and the chipset. And I don't mean what type of bus.
>>It's already known to be an HT link. So what's the name you want to give
>>it so that when someone refers to it by that name they will know exactly
>>which bus you are talking about and where it connects. And it has to be
>>specific. Sytem bus doesn't cut, there's many system buses. CPU bus
>>doesn't cut it as there are many cpu busses if you count the internal
>>busses. I say FSB. I'm waiting for a better one from you.

>
> AMD has used the term "I/O connection" when HT connects the CPU to an
> I/O chipset; before Pentium Pro it was called system bus or IIRC main
> bus or even main system bus.
>

So, I'm supposed to tell someone that the CPU clockspeed is determined by
the multiplier times the I/O connection speed. Right.:-) Would you care to
guess how many I/O connections there are in a basic PC system, 100,
1000, more than that?:-)

>>I'll give you two options. Take your pick. (1) The internal bus to the
>>L2 cache is the back side bus. It just internal now. (2) Why must there
>>be a BSB at all? FSB is more of a designation for a certain bus rather
>>than actually describing it's location. It connects between the CPU and
>>chipset, just as it did on the Athlon (non 64) cpu's. And no one had any
>>complaints of calling it a FSB then. That's what AMD called it.

>
> Again, the most important task of a FSB has been CPU<->memory traffic -
> the K8's HT doesn't do that... different topology... it's not an FSB.
>

Actually you can get a functioning system without external ssytem memory.
I'd sure like to see you use a system without a video output, or a storage
device, or any of the other functions that go over the FSB. They have
them, but they're usually used in standalone places as embedded. So, to
me, the memory is not the most important function, but even if it was,
it's still just ONE of many.

>>It makes all the sense in the world defined as the connection between
>>the CPU and chipset. If not, tell me what does. All you people have said
>>it's not right, yet none of you have come up with a definitive name for
>>the bus. I wonder if that's why it's stuck around so long, since I've
>>seen it defined as just that, the bus between the CPU and chipset.

>
> No it makes no sense at all, since by definition, as the cohort of a
> BSB, it carries CPU<->memory traffic. To belabor the point: the BSB
> carried CPU<->L2 Cache traffic and on cache misses, the traffic is
> "diverted" to FSB.
>

So, if it's not a FSB because the memory bus is now seperate, then the
memory bus is the FSB. Now I'm wondering what I'm going to call my car
when I take the removable dvd player out of it. Can't call it a car
anymore can I. Lost the cigar lighter, no more car.:-)

>>I don't know what you think a bus is. perhaps you should give your
>>definition of a bus, and not a school bus. Every definition of bus I've
>>seen says it an electrical pathway. So unless the HT link works without
>>electricty, it's a bus. As are all the others you claim aren't.

>
> You are (apparently) confused by an electrician's bus and a computer
> architect's bus. To some system experts/architects -- and there is at
> least one of them arguing with you -- the term "bus" implies "multi-drop
> bus", as is the case with Intel's GTL+ and AGTL+. It is also often used
> more loosely, as is the case of K7. When it is used with an
> accompanying qualifier, like PCI Bus, USB, FSB etc. it is generally a
> specific designation for something which is well, even formally, defined
> functionality. In K8, HT does not fulfill the same functionality as
> FSB.


And there's at least one system expert/architect that disagrees with
yours, namely me. Oh, and the HT people also disagree with your expert
also. But what do they know, they just develope it.
>
>>And now the killer punch. From;
>>
>>http://www.hypertransport.org/consortium/cons_faqs.cfm
>>
>>9. How does HyperTransport technology compare to other bus technologies?
>>
>>*****Read this pargraph carefully********
>> HyperTransport was designed to support both CPU-to-CPU
>>communications as well as CPU-to-I/O transfers, thus, it features very
>>low latency. Consequently, it has been incorporated into multiple x86
>>and MIPS architecture processors as an integrated front-side bus. *And
>>don't miss this................................. ^^^^^^^^^ *
>>
>>I rest my case.;-)

>
> What can I say?... somebody blundered... it's only a FAQ and


No kidding, and it was you.

> "*integrated* front side bus" is the only place where it refers to HT as
> a "bus".


Well, if it's a bus in one place, what is it in another? A motorcycle
maybe. Hmmm... it connects to the cpu and chipset just like other buses
did, so that means it can't be a bus.:-)

> If you look at
> http://www.amd.com/us-en/assets/cont...ure_FINAL2.pdf
> on p8 you'll find "Replacing what has traditionally been the system
> 'front-side bus' with a HyperTransport technology-based I/O connection
> dramatically extends processor to system communication bandwidth from
> 2.1GB/s up to 6.4GB/s". There are pictures for you of the old FSB
> architecture and the new HT-based architecture. Then on p9:
> "HyperTransport technology provides a high-speed, chip-to-chip
> interconnect..."


Sorry, my K8 system isn't designed the same way as it is in the diagram
you reference, and I doubt yours is either. Look at it closely. look at
the northbridge, and then look at the other side. What's changed other
than the name? One thing, the memory bus moved to the cpu. Now look at the
southbridge and then the other side. What's cahnged other than the name?
NOTHING. the chipset makers didn't adhere to these name changes either.
I've got a nortbridge and southbrige chipset, and there isn't any HT link
between them on my system. Basically, all they are saying is they replaced
the traditional (for AMD) EV6 FSB with an HT Link FSB. Although they do
show it going from the north to the southbridge, which isn't the case with
most chipsets. If you want to see the architecture of your chipset go to
their website. Mine uses multitol between the two. VIA uses something
else, and I'm sure each has their own bus type between the 2 devices.

Let's see. I've proven the HT link can be a bus. I've proven the HT link
is a FSB when connected betwen the cpu and chipset. That's it for me. if
you need proof from someone other than the people that develope HT
technology you'll have to get it elsewhere. Although if Ford tells me they
build cars, and someone else tells me they don't. I think I'd have to
believe Ford.

--
KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
Need good help? Provide all system info with question.
My server http://wesnewell.no-ip.com/cpu.php
Verizon server http://mysite.verizon.net/res0exft/cpu.htm

 
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Tony Hill
Guest
Posts: n/a
 
      10th Sep 2005
On Fri, 09 Sep 2005 04:52:36 GMT, Wes Newell
<(E-Mail Removed)> wrote:
>> People also still call the memory controller the "northbridge" and the
>> I/O chip a "southbridge", which also makes no sense given that they are
>> no longer being connected via PCI and they usually aren't bridges at
>> all. Again, just because people incorrectly use a term doesn't make it
>> correct.
>>

>What? The northbridge has much more in it than just a memory controller.
>And the K8 northbridge doesn't even have a memory controller in it.


It's also not a bridge nor is it 'north' (or 'south') of anything.
The term "northbridge" and "southbridge" come specifically from
definitions of PCI bridges. None of today's chipsets use PCI to
interconnect their two (or more) ICs that make up their motherboards
chipsets.

>> Yes, but that still doesn't make a goose a duck, even if lots of people
>> mix the two of them up.
>>

>Just out of curiosty, I'd like you to tell me what the name of the bus
>is between the CPU and the chipset.


Typically I refer to it exactly as it is: "CPU to chipset bus".

>> Hypertransport is NOT an 'bus' in any way, shape or form. HT is a
>> point-to-point link. PCI-E and AGP are also definitely not buses,
>> though I expect many people to incorrectly call them such. PCI and ISA
>> are buses

>
>I don't know what you think a bus is. perhaps you should give your
>definition of a bus, and not a school bus. Every definition of bus I've
>seen says it an electrical pathway. So unless the HT link works without
>electricty, it's a bus. As are all the others you claim aren't.
>
>And now the killer punch. From;
>
>http://www.hypertransport.org/consortium/cons_faqs.cfm
>
>9. How does HyperTransport technology compare to other bus technologies?
>
>As compared to older multidrop, shared buses such as PCI, PCI-X or SysAD,
>HyperTransport provides a far simplier electrical interface, but with much
>greater bandwidth. Instead of a wide, address/data/control multidrop,
>shared bus such as implemented by PCI, PCI-X or SysAD technologies,
>HyperTransport deploys narrow, but very fast unidirectional links to carry
>both data and command information encoded into packets. Unidirectional
>links provide significantly better signal integrity at high speeds and
>enable much faster data transfers with low-power 1.2V LVDS signals. In
>addition, link widths can be asymmetrical, meaning that 2 bit wide links
>can easily connect to 8 bit wide links and 8 bit wide links can connect to
>16 or 32 bit wide links and so on. Thus, the HyperTransport Technology
>eliminates the problems associated with high speed parallel buses with
>their many noisy bus signals (multiplexed data/address, and clock and
>control signals) while providing scalable bandwidth wherever it is needed
>in the system. As compared to newer serial I/O technologies such as
>RapidIO and PCI Express, HyperTransport shares some raw bandwidth
>characteristics, but is significantly different in some key
>characteristics.
>*****Read this pargraph carefully********


Err, and where exactly does it say that this is a bus? It says that
it REPLACES buses. From your link above:

<quoting>

7. What is HyperTransport technology?

HyperTransport chip-to-chip interconnect technology is a highly
optimized, high performance and low latency board-level architecture
for embedded and open- architecture systems. It provides up to 22.4
Gigabyte/second aggregate CPU to I/O or CPU to CPU bandwidth in a
highly efficient chip-to-chip technology that replaces existing
complex multi-level buses.

<end quote>


"I/O Link", "chip-to-chip interconnect" and "chip-to-chip technology"
are all used to describe it. Not "bus" because it isn't a bus.

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca
 
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Tony Hill
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      10th Sep 2005
On Fri, 09 Sep 2005 11:29:38 -0400, keith <(E-Mail Removed)> wrote:

>On Thu, 08 Sep 2005 21:41:35 -0400, Tony Hill wrote:
>
>> On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell
>> <(E-Mail Removed)> wrote:
>>
>> Not true at all. The original AMD Athlon had both a front-side bus,
>> connecting the CPU to the chipset, I/O and memory, and a backside bus
>> that connected the CPU to the cache chips on the Slot-A cartridge.
>> This was actually the last x86 CPU that I'm aware of which did have a
>> frontside bus (Intel had already gone to integrated cache by this
>> time).

>
>Just because the cache is integrated doesn't mean the cache isn't on the
>"back side" of the processor. The "back-side" concept was really a
>separation of the cache from the memory busses.


Ok, I'll grant that point. I would still say that it's not really an
accurate way of describing things when your 'bus' is connecting one
half of a die to the other half of the die, but I suppose it is still
a 'bus' of sorts, and certainly would be on the "backside" (relative
to memory).

-------------
Tony Hill
hilla <underscore> 20 <at> yahoo <dot> ca
 
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keith
Guest
Posts: n/a
 
      10th Sep 2005
On Sat, 10 Sep 2005 02:43:11 +0000, Wes Newell wrote:

> On Fri, 09 Sep 2005 18:23:25 -0400, George Macdonald wrote:
>
>> On Fri, 09 Sep 2005 04:52:36 GMT, Wes Newell <(E-Mail Removed)>
>> wrote:
>>>You're out to lunch here for the most part.

>>
>> If you go look up some tech docs & data sheets you'll find that he's spot
>> on... as usual. EV6 is not a bus by the usual criteria.
>>

> Suggest you read this. One of thousands that claim it's a bus.


I suggest you understand what a bus is, and forget what the popular press
says.

> http://www.free-definition.com/Front-side-bus.html


Yawn.

>>>Wrong. FSB is defined as the bus connection between the CPU and
>>>chipset. AMD calls the bus a FSB and I'm pretty sure Intel did too on
>>>the P4.

>>
>> You'll have to cite a technical reference for AMD calling the HT link
>> to the I/O chip(s) a FSB - brewing up your own folksy lexicon for
>> computer sub-system nomenclature will not do it.
>>

> I'm not wasting any more time citing crap for you. The proof is down
> below, which you tend to ignore.


There is no such "proof". The definition of a "bus" is much older than
even you. A buss is a multi-drop utility. ...kinda like what you take to
work. A point-to-point facility is never referred to as a "bus".

>>> If
>>>you break down the term, it's pretty simple. Front side, meaning not
>>>the back side, and bus. A bus is a collection of 1 or more electrical
>>>connections between 2 or more points. The type of bus (standard, EV6,
>>>HT link, or any other type) is of no concern.

>>
>> If we allow a bit of slack and call the on-die L2 cache connection a
>> BSB, we can call the K7s', P4s', P-Ms' connection to the chipset a FSB
>> - after all it carries the same traffic as a FSB. AMD has used this
>> terminology for its K7 architecture though some have argued with that.
>> With the K8 the HT link to to the I/O sub-system, however, there is no
>> CPU<-> memory traffic, which is the principal function of a FSB and is
>> the derivation of the name; the up/down HT link doesn't even serve the
>> same functions as a FSB.
>>

> The cpu to system memory function was just one of many functions the FSB
> does.


Nope. As you've been told a hundred times now, the FSB was so named
because Intel broke off the L2 cache from the system bus, and named the
cache interface the "back-side bus", this the memory and I/O bus became
the "front side". Those descriptions no longer fit the K8 system
architecture, so are discarded. ...no matter what the nitwits in the
popular press say.

> it still has cpu to memory functions and feeds data to/from the
> memory on the video card,


That's an I/O function.

> the cache memory on each hard drive


You really are stretching things thin.

> memory on other cards, etc, etc, etc.


What cards? Memory mapped I/O? PLease! That's still I/O.

>>>What? The northbridge has much more in it than just a memory
>>>controller. And the K8 northbridge doesn't even have a memory
>>>controller in it.

>>
>> <cough><splutter> You just fell in.
>>

> I meant the chipset northbridge.


You fell in again.

>> The K8 architecture does not have a north bridge... and in the case of
>> nForce3/4 has only the one chip for I/O and AGP/PCI-e Tunnel.
>>
>>>Well, AMD and Intel disagree, as do I. ANd it's used for one purpose
>>>IMO, to distinquish which fricking bus you are talking about.

>>
>> I won't argue about K7/P4/P-M but for K8.... references.
>>

> You already seen them from the Hyprtansport Consortium. Who do you want
> them from before you will believe it, God? Sorry, can't help you there.


You're the one who needs help! ...lots of it!

>>>Just out of curiosty, I'd like you to tell me what the name of the bus
>>>is between the CPU and the chipset. And I don't mean what type of bus.
>>>It's already known to be an HT link. So what's the name you want to
>>>give it so that when someone refers to it by that name they will know
>>>exactly which bus you are talking about and where it connects. And it
>>>has to be specific. Sytem bus doesn't cut, there's many system buses.
>>>CPU bus doesn't cut it as there are many cpu busses if you count the
>>>internal busses. I say FSB. I'm waiting for a better one from you.

>>
>> AMD has used the term "I/O connection" when HT connects the CPU to an
>> I/O chipset; before Pentium Pro it was called system bus or IIRC main
>> bus or even main system bus.
>>

> So, I'm supposed to tell someone that the CPU clockspeed is determined
> by the multiplier times the I/O connection speed. Right.:-) Would you
> care to guess how many I/O connections there are in a basic PC system,
> 100, 1000, more than that?:-)


Depending on the architecture... But to say it's a FSB is simply *WRONG*.

>>>I'll give you two options. Take your pick. (1) The internal bus to the
>>>L2 cache is the back side bus. It just internal now. (2) Why must there
>>>be a BSB at all? FSB is more of a designation for a certain bus rather
>>>than actually describing it's location. It connects between the CPU and
>>>chipset, just as it did on the Athlon (non 64) cpu's. And no one had
>>>any complaints of calling it a FSB then. That's what AMD called it.

>>
>> Again, the most important task of a FSB has been CPU<->memory traffic -
>> the K8's HT doesn't do that... different topology... it's not an FSB.
>>

> Actually you can get a functioning system without external ssytem
> memory.


I'd like to see that! BIOS won't post without system memory. BEEEEP!

> I'd sure like to see you use a system without a video output, or
> a storage device, or any of the other functions that go over the FSB.


No problem. Many servers have no video cards, keyboards, nor mice.
Storage devices are optional too (thin clients anyone), but memory isn't.
....not sure what your point is though (you have none; you loose).

> They have them, but they're usually used in standalone places as
> embedded. So, to me, the memory is not the most important function, but
> even if it was, it's still just ONE of many.


Really? Without memory nothing works. That's hardly the point though.
The micro-architecture of systems has changed; so does the terminology.
Is this *really* that hard for you to comprehend?

>>>It makes all the sense in the world defined as the connection between
>>>the CPU and chipset. If not, tell me what does. All you people have
>>>said it's not right, yet none of you have come up with a definitive
>>>name for the bus. I wonder if that's why it's stuck around so long,
>>>since I've seen it defined as just that, the bus between the CPU and
>>>chipset.

>>
>> No it makes no sense at all, since by definition, as the cohort of a
>> BSB, it carries CPU<->memory traffic. To belabor the point: the BSB
>> carried CPU<->L2 Cache traffic and on cache misses, the traffic is
>> "diverted" to FSB.
>>

> So, if it's not a FSB because the memory bus is now seperate, then the
> memory bus is the FSB.


No, the FSB was named such because it was *not* the back-side cache bus.

> Now I'm wondering what I'm going to call my car
> when I take the removable dvd player out of it. Can't call it a car
> anymore can I. Lost the cigar lighter, no more car.:-)


My guess is that you are as stupid as you make yourself out to be. Go
figure.

>>>I don't know what you think a bus is. perhaps you should give your
>>>definition of a bus, and not a school bus. Every definition of bus I've
>>>seen says it an electrical pathway. So unless the HT link works without
>>>electricty, it's a bus. As are all the others you claim aren't.

>>
>> You are (apparently) confused by an electrician's bus and a computer
>> architect's bus. To some system experts/architects -- and there is at
>> least one of them arguing with you -- the term "bus" implies
>> "multi-drop bus", as is the case with Intel's GTL+ and AGTL+. It is
>> also often used more loosely, as is the case of K7. When it is used
>> with an accompanying qualifier, like PCI Bus, USB, FSB etc. it is
>> generally a specific designation for something which is well, even
>> formally, defined functionality. In K8, HT does not fulfill the same
>> functionality as FSB.

>
> And there's at least one system expert/architect that disagrees with
> yours, namely me. Oh, and the HT people also disagree with your expert
> also. But what do they know, they just develope it.


Oh, and what would your credentials be to call yourself a system "expert"
or *architect*? You've certainly shown no such expertice here! The HT
architects certainly do *not* call the HT a bus, nor a front-side
*anything*.

<snip - bedtime; zzzzzzz>

--
Keith

 
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