Geek.com Geek News - AMD's quad-core CPUs will also sport L3 cache
http://www.geek.com/news/geeknews/20...1116033332.htm

Looks like the L3 cache is more like the buffer in a network switch. It
will keep data localized as much as possible to prevent too much cache
coherency traffic from going out unnecessarily.

Yousuf Khan

YKhan wrote:
> Geek.com Geek News - AMD's quad-core CPUs will also sport L3 cache
> http://www.geek.com/news/geeknews/20...1116033332.htm
>
> Looks like the L3 cache is more like the buffer in a network switch. It
> will keep data localized as much as possible to prevent too much cache
> coherency traffic from going out unnecessarily.
>
> Yousuf Khan
>

What I read elsewhere is that only the multiprocessor versions of
the 4-core chips will have the L3. Ie., 4c chips for 1P systems
will not have the L3.

Yeah, that would make sense to me. 1-socket/4-core systems wouldn't
have much external cache coherency traffic to worry about.

Yousuf Khan