Yes, that is pretty much the way I understand it. The charge is
necessary to invert the channel, that is have enough minority carriers
to make a layer of material look like it has become the opposite of what
it usually is. ie, change P type material to N type.
There is a lot of stuff with bands and potential wells if you are so
inclined. But that is basically it.
As for the gate capacitance, there is overlap capacitance and fringing
fields etc that are other components that don't go into inverting the
channel.
Robert Myers wrote:
> Let's see. You can tell me if this is wrong. To make the channel
> conducting, you have to move a certain amount of charge, q, to the
> vicinity of the gate, in effect, charging the capacitor that is the
> made by the channel, the insulating layer, and the gate electrode.
> q=CV. Lower C means higher V, meaning (I am guessing) that you have
> to raise the gate voltage, something you don't want. Thickening the
> insulating layer lowers C, a higher dielectric constant raises it.
> Higher dielectric constant allows you to thicken the layer of
> insulation without lowering C.
>
> What had me confused is that it had seemed to me that gate capacitance
> is something you *don't* want, since the time to charge the gate is
> the fundamental limit to the speed of operation of the transistor.
> Finally I realized that the amount of charge you have to move is a
> property of the conducting channel and not of the gate. At least, if
> I've got the story straight.
>
> Robert.
>
>
> On Jan 28, 4:52 pm, "Del Cecchi" <delcecchioftheno...@gmail.com>
> wrote:
>
>>"Robert Myers" <rbmyers...@gmail.com> wrote in messagenews:(E-Mail Removed)...
>>
>>
>>>On Jan 28, 12:04 am, Yousuf Khan <bbb...@yahoo.com> wrote:
>>
>>>>Why is this supposed to be such a big deal as compared to some of the
>>>>other developments from years gone by, like copper interconnects, and
>>>>SOI, and strain?
>>
>>>Becuase it gives you two things you want at the same time: reduced
>>>power consumption and faster operation--goals that had come to seem
>>>mutually incompatible. From my perspective, the reduced power
>>>consumption is the more important one. The main constraint on the
>>>kind of computing that interests me most is computational density,
>>>which is in turn constrained by power consumption. This is really
>>>good news for computational physics.
>>
>>>SOI, copper interconnect and even strained silicon seem possible to
>>>understand without a deep understanding of solid state physics. The
>>>ideas may not be obvious, but they seem at least natural. All the
>>>natural ideas, though, seemed to have pretty well run their course,
>>>and it looked like the chip alchemists were out of tricks.
>>
>>>Not so, apparently, and for reasons I think I'll have to do an awful
>>>lot of reading to understand. At the moment, it looks like a game-
>>>changer.
>>
>>>Robert.dood, it's simple. using poly silicon and silicon dioxide works really
>>
>>well until the oxide thickness is so thin that tunneling (you remember
>>tunneling right? that heisenberg thing?) causes a bunch of leakage right
>>through the supposed gate insulator. Now if you had a gate insulator
>>that had a higher dielectric constant you could make it thicker, take out
>>the tunneling, and still have the same electric field at the silicon
>>surface. And if the gate material were something with a different work
>>function then you could make the insulator even thicker. Ta Da. QED etc.
>>
>>The hard part is finding something that you can actually use to build
>>real transistors in a manufacturing environment.
>>
>>It ain't the phyics, exactly. Its the chemistry and the mechanics.
>>
>>del
>
>
--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.”
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