In article <Xns9714C113B5029bubbachipsetone@130.133.1.4>, Bubba
<(E-Mail Removed)> wrote:
> Greetings to all,
>
> I came across a 72 pin memory module that has 24 chips (12 per side). To
> be more precise, it has 24 Siemens HYB511000BJ-70 chips on itself with no
> additional IC-s. Used a bit of Google and came across this:
>
> Newsgroups: comp.sys.ibm.ps2.hardware
> Date: 1999/11/20
> Subject: Re: Help! Fake out a 79F1004!
> ...
> "That's an 8MB / 70ns 40-bit ECC module intended for the Server 95A."
> ...
> "ECC memory use a different approach for the error-detection and
> correction (!): they have 32 data bits (as parity have) grouped in 4 x
> 8 bits - but the 4 x 2 additional bits are used different."
>
> Well, I've seen ECC/parity modules with 9 or 17 chips (usually, 2^n+1
> chip). However, further in thread, someone mentioned term "ECC over
> parity" or "ECC-P". Unfortunately, Google was no use in this case. In
> addition to all that, IBM PS/2 Server 95A is being mentioned as a machine
> that accepts and works with that type of memory, but i can't seem to find
> any relevant documentation or datasheet about that computer.
>
> So, can anyone confirm the "40-bit ECC" thing and how it works (AFAIK, ECC
> corrects only 1 bit error and detects 2-bit whilst parity only detects 1-
> bit errors) and "ECC over parity" thing. Also, are parity/ECC modules,
> when observed "stand alone", equal, but parity/ECC functionality depends
> on chipset implementation?
>
> TIA!
According to this, a 72 pin SIMM has a 32 bit data bus. It also has
4 parity bits, which would be 1 bit per byte lane.
http://home.fuse.net/Walts_Place/memory72pin.htm
Maybe there are two chip types on the module ? I can
make a 12 chip bank, with a parity bit per lane, like this:
lane 0 lane 1 lane 2 lane 3
x4 x4 x1 x4 x4 x1 x4 x4 x1 x4 x4 x1
Individual x1 chips are used, when the processor supports byte
and half-word writes to memory - you only want to strobe one or
two lanes, and not update the parity bit on the other lanes.
(In fact, there were some special x4 chips made, which had four
independent x1 bits with their own strobes, just to allow the
construction of more compact modules for non-computer applications.)
The other kind of error correcting codes are Hamming codes,
like SECDED (single error correction, double error detection).
For example, the Athlon64 support a 64/8 code for use with 72 bit
wide DIMMs. (See page 136). They also have an alternative code, that
works in "dual channel mode", a 128/16 code called SSCDSD. It
apparently corrects a nibble, and is good for DIMMs with x4
chips on it. It allows a whole x4 chip to be dead, on a pair of
DIMMs, and still work.
http://www.amd.com/us-en/assets/cont...docs/26094.PDF
Generally, it takes one extra bit, for each doubling of the width
of the memory. That is why in this project, they use 6 bits to
protect 16 bits of information. So a 7 bit SECDED ECC looks good for a
32 bit wide memory.
http://www.personal.psu.edu/users/m/...nal_report.pdf
Paul
Similar Threads
