X-bit labs - AMD Thinks Triple-Core Microprocessors – Rumours.
"The new triple-core microprocessors will feature the same silicon as
quad-core chips, but with one core disabled. Nevertheless, the chips
will still include 2MB of shared L3 cache and will take advantage of
other K10 micro-architecture features, such as SSE4A instruction set,
128-bit floating point units (FPU) and so on. Obviously, the chips will
also have advanced power management capabilities."
http://www.xbitlabs.com/news/cpu/dis...914212726.html

AMD prepares three-core processors
"AMD is probably doing this for two reasons; the lesser being salvage,
the more important one being that Intel can't do it. Intel would have a
far harder time making a tri-core part until Nehalem next September - it
is easy to fuse off a core, far harder to MCM disparate cores."
http://www.theinquirer.net/default.aspx?article=42369

On Sat, 15 Sep 2007 13:40:17 -0400, Yousuf Khan <(E-Mail Removed)> wrote:

>X-bit labs - AMD Thinks Triple-Core Microprocessors – Rumours.
>"The new triple-core microprocessors will feature the same silicon as
>quad-core chips, but with one core disabled. Nevertheless, the chips
>will still include 2MB of shared L3 cache and will take advantage of
>other K10 micro-architecture features, such as SSE4A instruction set,
>128-bit floating point units (FPU) and so on. Obviously, the chips will
>also have advanced power management capabilities."
>http://www.xbitlabs.com/news/cpu/dis...914212726.html
>
>AMD prepares three-core processors
>"AMD is probably doing this for two reasons; the lesser being salvage,
>the more important one being that Intel can't do it. Intel would have a
>far harder time making a tri-core part until Nehalem next September - it
>is easy to fuse off a core, far harder to MCM disparate cores."
>http://www.theinquirer.net/default.aspx?article=42369


Yeah...well, ok, but a partial is a partial no matter why it exists ;-)

/daytripper
(not that it's necessarily a *bad* thing, but let's call it what it is)

daytripper <(E-Mail Removed)> wrote:
: On Sat, 15 Sep 2007 13:40:17 -0400, Yousuf Khan
: <(E-Mail Removed)> wrote:
:
:: X-bit labs - AMD Thinks Triple-Core Microprocessors - Rumours.
:: "The new triple-core microprocessors will feature the same
:: silicon as quad-core chips, but with one core disabled.
:: Nevertheless, the chips will still include 2MB of shared L3
:: cache and will take advantage of other K10 micro-architecture
:: features, such as SSE4A instruction set, 128-bit floating
:: point units (FPU) and so on. Obviously, the chips will also
:: have advanced power management capabilities."
:: http://www.xbitlabs.com/news/cpu/dis...914212726.html
::
:: AMD prepares three-core processors
:: "AMD is probably doing this for two reasons; the lesser being
:: salvage, the more important one being that Intel can't do it.
:: Intel would have a far harder time making a tri-core part
:: until Nehalem next September - it is easy to fuse off a core,
:: far harder to MCM disparate cores."
:: http://www.theinquirer.net/default.aspx?article=42369
:
:
: Yeah...well, ok, but a partial is a partial no matter why it
: exists ;-)
:
: /daytripper
: (not that it's necessarily a *bad* thing, but let's call it
: what it is)

Heh heh. Isn't this simply called "bining" <sp?>?

G7

On Sat, 15 Sep 2007 21:06:42 +0200, "Gary Seven" <(E-Mail Removed)> wrote:

>daytripper <(E-Mail Removed)> wrote:
>: On Sat, 15 Sep 2007 13:40:17 -0400, Yousuf Khan
>: <(E-Mail Removed)> wrote:
>:
>:: X-bit labs - AMD Thinks Triple-Core Microprocessors - Rumours.
>:: "The new triple-core microprocessors will feature the same
>:: silicon as quad-core chips, but with one core disabled.
>:: Nevertheless, the chips will still include 2MB of shared L3
>:: cache and will take advantage of other K10 micro-architecture
>:: features, such as SSE4A instruction set, 128-bit floating
>:: point units (FPU) and so on. Obviously, the chips will also
>:: have advanced power management capabilities."
>:: http://www.xbitlabs.com/news/cpu/dis...914212726.html
>::
>:: AMD prepares three-core processors
>:: "AMD is probably doing this for two reasons; the lesser being
>:: salvage, the more important one being that Intel can't do it.
>:: Intel would have a far harder time making a tri-core part
>:: until Nehalem next September - it is easy to fuse off a core,
>:: far harder to MCM disparate cores."
>:: http://www.theinquirer.net/default.aspx?article=42369
>:
>:
>: Yeah...well, ok, but a partial is a partial no matter why it
>: exists ;-)
>:
>: /daytripper
>: (not that it's necessarily a *bad* thing, but let's call it
>: what it is)
>
>Heh heh. Isn't this simply called "bining" <sp?>?

Kinda, though as classically used wrt semiconductors, "binning" means
"functionally identical but with differing speed".

This is much more like the old "partially good" semiconductor memories sold by
foundries on the cheap to companies that could find ways to use the good areas
of the arrays and avoid the defective regions (for just one example, the solid
state disks sold by DEC in the '90s, which combined a robust ecc code with
strategically applied array addressing).

As a marketing message, I really don't think "We can make devices that are 75%
functional" is going to sway many Intelophiles...

/daytripper (but then, I could be wrong ;-)

On a sunny day (Sat, 15 Sep 2007 16:09:04 -0400) it happened daytripper
<(E-Mail Removed)> wrote in
<(E-Mail Removed)>:

>As a marketing message, I really don't think "We can make devices that are 75%
>functional" is going to sway many Intelophiles...
>
>/daytripper (but then, I could be wrong ;-)

IBM does the same with Cell in PS3.
It just differentiates to a more granular price scale.

In article <fchg7t$6bg$(E-Mail Removed)>, (E-Mail Removed)
says...
> On a sunny day (Sat, 15 Sep 2007 16:09:04 -0400) it happened daytripper
> <(E-Mail Removed)> wrote in
> <(E-Mail Removed)>:
>
> >As a marketing message, I really don't think "We can make devices that are 75%
> >functional" is going to sway many Intelophiles...

100% good ones catching fire wouldn't help their marketing plans
either.

> >/daytripper (but then, I could be wrong ;-)

Never!

> IBM does the same with Cell in PS3.
> It just differentiates to a more granular price scale.

IBM has done it since forever (I saw it first in memories in the
'70s). The Z8 had ten processors. The processors you didn't pay for
were disabled by the crypto hardware. If one of the enabled ones
died another took over. If you needed more MIPS to do your taxes
this month, simply call you friendly salesman and buy/rent another
processor, or eight, and the mothership would download the
appropriate cryptographically protected microcode to enable the
processors for the time needed (a.k.a. "Dial-A-MIP").

--
Keith

daytripper wrote:
> Yeah...well, ok, but a partial is a partial no matter why it exists ;-)

Well, these days the dual-cores are becoming the low-end, so if quads
are the high-end, then something has to fill the middle. You could try
to fill the middle with faster duals, or slower quads, or you could just
as well try selling tri-cores. Voila, Marquetting!

On Sun, 16 Sep 2007 20:46:26 -0400, Yousuf Khan <(E-Mail Removed)> wrote:

>daytripper wrote:
>> Yeah...well, ok, but a partial is a partial no matter why it exists ;-)
>
>Well, these days the dual-cores are becoming the low-end, so if quads
>are the high-end, then something has to fill the middle. You could try
>to fill the middle with faster duals, or slower quads, or you could just
>as well try selling tri-cores. Voila, Marquetting!

Well, here is a test for you then: assuming there is *some* premium for a
triple core vs an otherwise comparable dual core, would you buy the former?

/daytripper

In article <(E-Mail Removed)>,
(E-Mail Removed) says...
> On Sun, 16 Sep 2007 20:46:26 -0400, Yousuf Khan <(E-Mail Removed)> wrote:
>
> >daytripper wrote:
> >> Yeah...well, ok, but a partial is a partial no matter why it exists ;-)
> >
> >Well, these days the dual-cores are becoming the low-end, so if quads
> >are the high-end, then something has to fill the middle. You could try
> >to fill the middle with faster duals, or slower quads, or you could just
> >as well try selling tri-cores. Voila, Marquetting!
>
> Well, here is a test for you then: assuming there is *some* premium for a
> triple core vs an otherwise comparable dual core, would you buy the former?

Define "otherwise comparable"? Is there a benefit? Why would I buy
a dual if a single was "otherwise comparable"?

--
Keith

On Sun, 16 Sep 2007 23:35:04 -0400, krw <(E-Mail Removed)> wrote:

>In article <(E-Mail Removed)>,
>(E-Mail Removed) says...
>> On Sun, 16 Sep 2007 20:46:26 -0400, Yousuf Khan <(E-Mail Removed)> wrote:
>>
>> >daytripper wrote:
>> >> Yeah...well, ok, but a partial is a partial no matter why it exists ;-)
>> >
>> >Well, these days the dual-cores are becoming the low-end, so if quads
>> >are the high-end, then something has to fill the middle. You could try
>> >to fill the middle with faster duals, or slower quads, or you could just
>> >as well try selling tri-cores. Voila, Marquetting!
>>
>> Well, here is a test for you then: assuming there is *some* premium for a
>> triple core vs an otherwise comparable dual core, would you buy the former?
>
>Define "otherwise comparable"? Is there a benefit? Why would I buy
>a dual if a single was "otherwise comparable"?

Assume my awkward phrasing referred to cores of equal performance...

/daytripper