Charlie at the Inq is attempting to clear up the AMD quad-core roadmap,
removing all confusing stories (which mainly he himself started) about
the timetable for 4-core introduction. Although he tried to clear up
the confusion, I don't think that guy can write two sentences without
them contradicting each other. Hard skill to acquire, even harder to
get rid of. So I'll summarize even more, and then you can go and read
the article:

-2007Q2: Barcelona core, Rev. H (aka K8L), HT2.0
-2007Q4: Budapest core, same Rev. H, HT3.0 for Socket AM2.
-2008Q1: Shanghai core, same as Budapest core for Socket F.

Apparently the big news here is the introduction of HT3.0. It's a big
enough change that it expects its partners to miss chipset introduction
schedules, getting products out to take advantage of the new interface.
So it's initially going to introduce Rev H with an old-fashioned HT2.0
interface. So it'll synchronize introduction of the Budapest and
Shanghai when all partners are ready with their appropriate products,
but in the meantime we'll still be able to see Rev. H in action.

AMD quad cores: the whole story unfolded
"Barcelona, Shanghai, Budapest and 65 nanometre"
http://www.theinquirer.net/default.aspx?article=34433

On 16 Sep 2006 18:23:58 -0700, "YKhan" <(E-Mail Removed)> wrote:


>Apparently the big news here is the introduction of HT3.0. It's a big
>enough change that it expects its partners to miss chipset introduction
>schedules, getting products out to take advantage of the new interface.

Huh?? A year+ isn't enough time to adjust to that??







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On 16 Sep 2006 18:23:58 -0700, "YKhan" <(E-Mail Removed)> wrote:

>Charlie at the Inq is attempting to clear up the AMD quad-core roadmap,
>removing all confusing stories (which mainly he himself started) about
>the timetable for 4-core introduction. Although he tried to clear up
>the confusion, I don't think that guy can write two sentences without
>them contradicting each other. Hard skill to acquire, even harder to
>get rid of.

Agreed, the guy can create more confusion in one para than anybody else
I've read.

> So I'll summarize even more, and then you can go and read
>the article:
>
>-2007Q2: Barcelona core, Rev. H (aka K8L), HT2.0
>-2007Q4: Budapest core, same Rev. H, HT3.0 for Socket AM2.
>-2008Q1: Shanghai core, same as Budapest core for Socket F.
>
>Apparently the big news here is the introduction of HT3.0. It's a big
>enough change that it expects its partners to miss chipset introduction
>schedules, getting products out to take advantage of the new interface.
>So it's initially going to introduce Rev H with an old-fashioned HT2.0
>interface. So it'll synchronize introduction of the Budapest and
>Shanghai when all partners are ready with their appropriate products,
>but in the meantime we'll still be able to see Rev. H in action.
>
>AMD quad cores: the whole story unfolded
>"Barcelona, Shanghai, Budapest and 65 nanometre"
>http://www.theinquirer.net/default.aspx?article=34433

I still don't get what is happening with dual-core?... if anything. Does
this mean that AMD has no planned dual-core part at 65nm... or just that
all parts will be targeted at quad-core and the duals will be the failed
quad parts? I *hope* this is wrong.

--
Rgds, George Macdonald

George Macdonald wrote:
> Agreed, the guy can create more confusion in one para than anybody else
> I've read.

<snip>

> I still don't get what is happening with dual-core?... if anything. Does
> this mean that AMD has no planned dual-core part at 65nm... or just that
> all parts will be targeted at quad-core and the duals will be the failed
> quad parts? I *hope* this is wrong.

See, there's Charlie-derived confusion already! :-)

I think all this means is that they're only talking about the plans for
4-core, since that's what most people are interested in. I'm sure the
dual-cores are coming out in Rev. H form too, but nobody is worried
about those.

Yousuf Khan

The Kat wrote:
> On 16 Sep 2006 18:23:58 -0700, "YKhan" <(E-Mail Removed)> wrote:
>
>
>> Apparently the big news here is the introduction of HT3.0. It's a big
>> enough change that it expects its partners to miss chipset introduction
>> schedules, getting products out to take advantage of the new interface.
>
> Huh?? A year+ isn't enough time to adjust to that??
>

Who knows, but AMD is apparently planning for it, by having the
contingency plan ready. Well, I guess you can't call it a contingency
plan, since it's actually the main plan. What's HT3.0 supposed to have
anyways that's not in HT2.0? The only thing I've heard about is that
it's going allow for Hypertransport cables to connect between system
boards. This seems mainly useful for server situations. What's it going
to be good for in the PC realm, other than being faster?

Yousuf Khan

--
There is no failure, only delayed success

On 17 Sep 2006 06:56:06 -0700, "YKhan" <(E-Mail Removed)> wrote:

>George Macdonald wrote:
>> Agreed, the guy can create more confusion in one para than anybody else
>> I've read.
>
> <snip>
>
>> I still don't get what is happening with dual-core?... if anything. Does
>> this mean that AMD has no planned dual-core part at 65nm... or just that
>> all parts will be targeted at quad-core and the duals will be the failed
>> quad parts? I *hope* this is wrong.
>
>See, there's Charlie-derived confusion already! :-)

I didn't think I was losing my interpretive skills... but.:-0 You must
have seen this one: http://www.theinquirer.net/default.aspx?article=33906
where after 6 paras or so of talking about quad-core he states: "Now, you
notice that covers 2C chips, what about QC/4C?"<gawp>

>I think all this means is that they're only talking about the plans for
>4-core, since that's what most people are interested in. I'm sure the
>dual-cores are coming out in Rev. H form too, but nobody is worried
>about those.

I just hope that the dual cores are not going to be squeezed on L2 cache so
that four cores can fit on a die. Personally I'm *not* "interested" - I
fail to see how four cores is going to be a big advantage to anybody on
desktop; software is going to take years to catch up, if ever. I'm
beginning to think I *might* be disappointed by AMD's first 65nm efforts.

--
Rgds, George Macdonald

George Macdonald wrote:
> I didn't think I was losing my interpretive skills... but.:-0 You must
> have seen this one: http://www.theinquirer.net/default.aspx?article=33906
> where after 6 paras or so of talking about quad-core he states: "Now, you
> notice that covers 2C chips, what about QC/4C?"<gawp>

Nah, didn't see that one, thank god. I'd say his latest piece of work
supercedes that one anyways. :-)

>> I think all this means is that they're only talking about the plans for
>> 4-core, since that's what most people are interested in. I'm sure the
>> dual-cores are coming out in Rev. H form too, but nobody is worried
>> about those.
>
> I just hope that the dual cores are not going to be squeezed on L2 cache so
> that four cores can fit on a die. Personally I'm *not* "interested" - I
> fail to see how four cores is going to be a big advantage to anybody on
> desktop; software is going to take years to catch up, if ever. I'm
> beginning to think I *might* be disappointed by AMD's first 65nm efforts.

What do you mean by "squeezed on L2 cache"?

Yousuf Khan

> What do you mean by "squeezed on L2 cache"?

I'd guess he means he hopes that AMD is not skimping on cache in favor
of extra cores. To be honest, I think that AMD would be fine with
512KB L2/core. The 1MB is obviously better, but I think performance
would be alright with 512KB/core, especially if there are robust
mechanisms for communication between the different caches.

To be honest, I'm pretty darn confused about AMD's roadmap myself. I
know there are quad cores out there next year toward the middle of the
year, but...that's all I'm sure of.

DK

On 18 Sep 2006 12:44:01 -0700, "David Kanter" <(E-Mail Removed)> wrote:

>> What do you mean by "squeezed on L2 cache"?
>
>I'd guess he means he hopes that AMD is not skimping on cache in favor
>of extra cores. To be honest, I think that AMD would be fine with
>512KB L2/core. The 1MB is obviously better, but I think performance
>would be alright with 512KB/core, especially if there are robust
>mechanisms for communication between the different caches.

Yep on the first comment.

Hmmm, to compete against Conroe and off-spring I think they have to
consider bigger than 512KB; I'm still convinced that Conroe's most
spectacular performance is helped considerably by the 4MB available for
each core. With their exclusive caching scheme, I don't see a unified L2
being a practical route for AMD.

>To be honest, I'm pretty darn confused about AMD's roadmap myself. I
>know there are quad cores out there next year toward the middle of the
>year, but...that's all I'm sure of.

According to that latest "from the horse's mouth" Inquirer article, the
65nm Rev H core, in quad form, is in full line production now with finished
wafers expected in December. That would mean that 2Q07 is a reasonable
target for "availability" and that the 65nm Rev F shrink was a red
herring... but then again, you always have to read between Charlie's
(garbled) lines.:-)

--
Rgds, George Macdonald

> >> What do you mean by "squeezed on L2 cache"?
> >
> >I'd guess he means he hopes that AMD is not skimping on cache in favor
> >of extra cores. To be honest, I think that AMD would be fine with
> >512KB L2/core. The 1MB is obviously better, but I think performance
> >would be alright with 512KB/core, especially if there are robust
> >mechanisms for communication between the different caches.
>
> Yep on the first comment.
>
> Hmmm, to compete against Conroe and off-spring I think they have to
> consider bigger than 512KB;

Remember, most conroes are 2MB, not 4MB. It would be sufficient to
have a couple of FX models with larger caches to compete with the
Conroe XE. Of course, I'm sure you're mention that 4x4 should take on
that role ; )

Obviously 1MB L2/core would be better, but I don't know how feasible
that is for a quad core part. I think that would be pretty unhappy for
the MFG guys.

> I'm still convinced that Conroe's most
> spectacular performance is helped considerably by the 4MB available for
> each core.

That is certainly a component. However, I think there are a lot of
other factors. The folks I know are *very* impressed by the
prefetching capabilities.

> With their exclusive caching scheme, I don't see a unified L2
> being a practical route for AMD.

It would eat up a lot of bandwidth, yes. It's unclear to me exactly
how they plan to do the L3 cache. I like caches with write-through
(i.e. inclusion) a lot for the purposes of coherency, which is of
growing importance for CMP designs. However, I think non-exclusive,
non-inclusive caches are fine too (replicate L1 tags for the same
effect). Exclusive caches I don't really like much because I feel it
gives up a lot on bandwidth. Another problem is that generally you
want different levels of the cache hierarchy to be at least a factor of
8 larger/smaller in size for inclusion.

I don't think AMD wants to shrink their L1, which means they are stuck
with an exclusive L2 unless it's 1MB or larger.

DK