In article <(E-Mail Removed)>,
(E-Mail Removed) says...
> > > Two years. ATI has never targeted an SOI process, and they'd need to
> > > start using whatever CAD tools AMD uses internally. That's a pretty
> > > big shift, and it's not something you'd ever do in the middle of a
> > > project...
> >
> > There is no law that says ANMD *must* do SOI in Dresden.
>
> Well considering that AMD has stated they will be doing 'copy exact'...
One can do bulk CMOS on a line already set up for SOI, is my point.
> > Even if
> > they wanted to go with the current process, it's not that big of a
> > shift, at least for the logic designers.
>
> Yes, but if you've already started on any PD, you're going to need to
> redo that. I think from a project management standpoint it would be a
> pretty bad idea.
This "bad idea" has been done before.
> I would expect that if they wanted to switch over
> they would start with designs that haven't done much PD. My rough
> estimate is that the design time for a GPU is 3 years, and PD probably
> starts after 1 year. After they start PD, I don't think they'd
> retarget.
Have you ever *done* this? Me thinks you're talking though your
hat, again.
> > Pick one set of "books"
> > instead of another. Circuit design is different (presumably AMD
> > already has the necessary circuits), and processing is different,
> > but one logic chip looks pretty much like the next.
>
> AMD has the necessary circuits, but ATI engineers have no experience
> with them. That's just asking for trouble, even if you have AMD
> circuits guys coaching them along. Delays for CPUs are bad, but for
> GPUs they are brutal, since the life time is so much shorter.
One doesn't need "experience" with a circuit to use it. Logic is
logic, fer chrissake. The biggest problem with SOI is getting the
circuit designs right.
> > > Considering that GPUs take at least 3 years to design, I think the
> > > earliest that this could happen is 2 years from now (assuming that
> > > there is a design that started 6-12 months ago, and was still in
> > > architectural phase and hadn't done any actual physical stuff).
> >
> > It would take less than a year to migrate a design form bulk to a
> > mature SOI process.
>
> Can you elaborate? Do you mean a design that is already in bulk
> production? Or do you just mean a taped out bulk design?
Either way. Assuming no silicon (though metal changes may be
necessary) respins for logic errors, to SOI production volumes.
This would include hardware verification and perhaps two passes
(engineering then production) through silicon. The switch may be
transparent for a design already in the pipe, though logic errors
are an issue on a new design.
--
Keith