This is just extra publicity for what has already been
known for months, ie the drive to 65nm is on a fast
pace, things are looking good, much more straining of
silicon, better internal power management, etc. The really
exciting transistor designs will happen at 45nm, using the high-k
interconnects. Though that's still three years away. And there
is interesting research going on at 15nm, for the next decade.
What's not known is exactly how Intel is going to design
the silicon. How are the multiple cores going to work, especially
with the one bus? Even more significantly, how are applications going
to benefit from the 2+ cores; are they going to have to explicitly
code multiple-threading to benefit, which afterall ain't easy to pull off,
or will the feeding of the multiple cores be handled effectively by the
compilers,
or may be even the OS? I see that Intel has released a thread checking
tool, hopefully MS incorporates something like it in their next Studio.
So far, looks like the new upcoming multi-core chip designs will depend heavily
on how applications are developed, more so than ever before. We
already saw some of this with the branch-predictors, the results
weren't impressive at all. If the thread related logic issues can't somehow be
handled at the tool, OS, compiler, or chip level, then it's going to be a long
day reaping the full potential of 2+ cores. 2+ cores may end up like the
386, full of potential but not enough software support.
"Yousuf Khan" <(E-Mail Removed)> wrote in message
news:24zYc.102338$(E-Mail Removed)...
>
http://www.reuters.com/locales/c_new...toryID=6098883
>
> Yousuf Khan
>
>