3d partitioning of IC/PCBs

I thought this looked interesting:
http://ap.pennnet.com/Articles/Artic...ICLE_ID=220939

I dunno how well their eye "simulations" correspond to reality but it does
appear to bring a new perspective to circuit routing. In particular, with
the 4-chip interconnect diagram (fig. 5), is it just me, or does this look
like a future direction for AMD Opterons... with maybe a superHT for
inter-processor links? From what I see AMD's roadmaps seem to peg HT at
1000MHz base clock well into 2006 and it just doesn't seem good enough.

I'll be interested to hear what the hardware guys, like Keith, have to say
about this approach... i.e. is it really that good or practical
IC-packaging-wise? I wonder how those "super highways" really work?... are
they carrying signals only and how well does that work as they pass, in
close proximity, to other components on a PCB?

--
Rgds, George Macdonald